CMOS CIRCUITS MANUAL
CONTENTS CHAPTER 1 INTRODUCTION TO CMOS DESIGN 1 1 THE CMOS IC DESIGN PROCESS 1 1 1 FABRICATION LAYOUT AND CROSS-SECTIONAL VIEWS 1 2 CMOS BACKGROUND THE CMOS ACRONYM CMOS INVERTER THE FIRST CMOS CIRCUITS ANALOG DESIGN IN CMOS 1 3 AN INTRODUCTION TO SPICE GENERATING A NETLIST FILE OPERATING POINT TRANSFER FUNCTION ANALYSIS THE VOLTAGE-CONTROLLED VOLTAGE SOURCE AN IDEAL OP-AMP THE SUBCIRCUIT DC ANALYSIS PLOTTING IV CURVES DUAL LOOP DC ANALYSIS TRANSIENT ANALYSIS THE SIN SOURCE AN RC CIRCUIT EXAMPLE ANOTHER RC CIRCUIT EXAMPLE AC ANALYSIS DECADES AND OCTAVES DECIBELS PULSE STATEMENT FINITE PULSE RISE TIME STEP RESPONSE DELAY AND RISE TIME IN RC CIRCUITS PIECE-WISE LINEAR (PWL) SOURCE SIMULATING SWITCHES INITIAL CONDITIONS ON A CAPACITOR INITIAL CONDITIONS IN AN INDUCTOR Q OF AN LC TANK FREQUENCY RESPONSE OF AN IDEAL INTEGRATOR UNITY-GAIN FREQUENCY TIME-DOMAIN BEHAVIOR OF THE INTEGRATOR CONVERGENCE SOME COMMON MISTAKES AND HELPFUL TECHNIQUES CHAPTER 2 THE WELL THE SUBSTRATE (THE UNPROCESSED WAFER) A PARASITIC DIODE USING THE N-WELL AS A RESISTOR 2 1 PATTERNING 2 1 1 PATTERNING THE N-WELL 2 2 LAYING OUT THE N-WELL 2 2 1 DESIGN RULES FOR THE N-WELL 2 3 RESISTANCE CALCULATION LAYOUT OF CORNERS 2 3 1 THE N-WELL RESISTOR 2 4 THE N-WELL/SUBSTRATE DIODE 2 4 1 A BRIEF INTRODUCTION TO PN JUNCTION PHYSICS CARRIER CONCENTRATIONS FERMI ENERGY LEVEL 2 4 2 DEPLETION LAYER CAPACITANCE 2 4 3 STORAGE OR DIFFUSION CAPACITANCE 2 4 4 SPICE MODELING 2 5 THE RC DELAY THROUGH THE N-WELL RC CIRCUIT REVIEW DISTRIBUTED RC DELAY DISTRIBUTED RC RISE TIME 2 6 TWIN WELL PROCESSES DESIGN RULES FOR THE WELL SEM VIEWS OF WELLS CHAPTER 3 THE METAL LAYERS 3 1 THE BONDING PAD 3 1 1 LAYING OUT THE PAD I CAPACITANCE OF METAL-TO-SUBSTRATE PASSIVATION AN IMPORTANT NOTE 3 2 DESIGN AND LAYOUT USING THE METAL LAYERS AN EXAMPLE LAYOUT 3 2 2 PARASITICS ASSOCIATED WITH THE METAL LAYERS INTRINSIC PROPAGATION DELAY 3 2 3 CURRENT-CARRYING LIMITATIONS 3 2 4 DESIGN RULES FOR THE METAL LAYERS LAYOUT OF TWO SHAPES OR A SINGLE SHAPE A LAYOUT TRICK FOR THE METAL LAYERS 3 2 5 CONTACT RESISTANCE 3 3 CROSSTALK AND GROUND BOUNCE 3 3 1 CROSSTALK 3 3 2 GROUND BOUNCE DC PROBLEMS AC PROBLEMS A FINAL COMMENT 3 4 LAYOUT EXAMPLES 3 4 1 LAYING OUT THE PAD II 3 4 2 LAYING OUT METAL TEST STRUCTURES SEM VIEW OF METAL CHAPTER 4 THE ACTIVE AND POLY LAYERS 4 1 LAYOUT USING THE ACTIVE AND POLY LAYERS THE ACTIVE LAYER THE P- AND N-SELECT LAYERS THE POLY LAYER SELF-ALIGNED GATE THE FINFET THE POLY WIRE SILICIDE BLOCK 4 1 1 PROCESS FLOW DAMASCENE PROCESS STEPS 4 2 CONNECTING WIRES TO POLY AND ACTIVE CONNECTING THE P-SUBSTRATE TO GROUND LAYOUT OF AN N-WELL RESISTOR LAYOUT OF AN NMOS DEVICE LAYOUT OF A PMOS DEVICE A COMMENT CONCERNING MOSFET SYMBOLS STANDARD CELL FRAME DESIGN RULES 4 3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION LAYOUT OF THE DIODES CHAPTER 5 RESISTORS, CAPACITORS, MOSFETS 5 1 RESISTORS TEMPERATURE COEFFICIENT (TEMP CO) POLARITY OF THE TEMP CO VOLTAGE COEFFICIENT USING UNIT ELEMENTS GUARD RINGS INTERDIGITATED LAYOUT COMMON-CENTROID LAYOUT DUMMY ELEMENTS 5 2 CAPACITORS LAYOUT OF THE POLY-POLY CAPACITOR PARASITICS 5 3 MOSFETS LATERAL DIFFUSION OXIDE ENCROACHMENT SOURCE/DRAIN DEPLETION CAPACITANCE SOURCE/DRAIN PARASITIC RESISTANCE LAYOUT OF LONG-LENGTH MOSFETS LAYOUT OF LARGE-WIDTH MOSFETS A QUALITATIVE DESCRIPTION OF MOSFET CAPACITANCES 5 4 LAYOUT EXAMPLES METAL CAPACITORS POLYSILICON RESISTORS CHAPTER 6 MOSFET OPERATION 6 1 MOSFET CAPACITANCE OVERVIEW/REVIEW CASE I: ACCUMULATION CASE II: DEPLETION CASE III: STRONG INVERSION SUMMARY 6 2 THE THRESHOLD VOLTAGE CONTACT POTENTIALS THRESHOLD VOLTAGE ADJUST 6 3 IV CHARACTERISTICS OF MOSFETS 6 3 1 MOSFET OPERATION IN THE TRIODE REGION 6 3 2 THE SATURATION REGION CGS CALCULATION IN THE SATURATION REGION 6 4 SPICE MODELING OF THE MOSFET MODEL PARAMETERS RELATED TO VTHN LONG-CHANNEL MOSFET MODELS MODEL PARAMETERS RELATED TO THE DRAIN CURRENT SPICE MODELING OF THE SOURCE AND DRAIN IMPLANTS 6 4 1 SOME SPICE SIMULATION EXAMPLES THRESHOLD VOLTAGE AND BODY EFFECT 6 4 2 THE SUBTHRESHOLD CURRENT 6 5 SHORT-CHANNEL MOSFETS HOT CARRIERS LIGHTLY DOPED DRAIN (LDD) 6 5 1 MOSFET SCALING 6 5 2 SHORT-CHANNEL EFFECTS NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) OXIDE BREAKDOWN DRAIN-INDUCED BARRIER LOWERING GATE-INDUCED DRAIN LEAKAGE GATE TUNNEL CURRENT 6 5 3 SPICE MODELS FOR OUR SHORT-CHANNEL CMOS PROCESS BSIM4 MODEL LISTING (NMOS) BSIM4 MODEL LISTING (PMOS) SIMULATION RESULTS CHAPTER 7 CMOS FABRICATION 7 1 CMOS UNIT PROCESSES 7 1 1 WAFER MANUFACTURE METALLURGICAL GRADE SILICON (MGS) ELECTRONIC GRADE SILICON (EGS) CZOCHRALSKI (CZ) GROWTH AND WAFER FORMATION 7 1 2 THERMAL OXIDATION 7 1 3 DOPING PROCESSES ION IMPLANTATION SOLID STATE DIFFUSION 7 1 4 PHOTOLITHOGRAPHY RESOLUTION DEPTH OF FOCUS ALIGNING MASKS 7 1 5 THIN FILM REMOVAL THIN FILM ETCHING WET ETCHING DRY ETCHING CHEMICAL MECHANICAL POLISHING 7 1 6 THIN FILM DEPOSITION PHYSICAL VAPOR DEPOSITION (PVD) CHEMICAL VAPOR DEPOSITON (CVD) 7 2 CMOS PROCESS INTEGRATION FEOL BEOL CMOS PROCESS DESCRIPTION 7 2 1 FRONTEND-OF-THE-LINE INTEGRATION STARTING MATERIAL SHALLOW TRENCH ISOLATION MODULE TWIN TUB MODULE GATE MODULE SOURCE/DRAIN MODULE 7 2 2 BACKEND-OF-THE-LINE INTEGRATION SELF-ALIGNED SILICIDE (SALICIDE) MODULE PRE-METAL DIELECTRIC CONTACT MODULE METALLIZATION INTRA-METAL DIELECTRIC 1 DEPOSITION VIA 1 MODULE ADDITIONAL METAL/DIELETRIC LAYERS FINAL PASSIVATION 7 3 BACKEND PROCESSES WAFER PROBE DIE SEPARATION PACKAGING FINAL TEST AND BURN-IN 7 4 ADVANCED CMOS PROCESS INTEGRATION 7 4 1 FINFETS 7 4 2 DUAL DAMASCENE LOW-K/CU INTERCONNECTS 7 5 SUMMARY CHAPTER 8 ELECTRICAL NOISE: AN OVERVIEW 8 1 SIGNALS 8 1 1 POWER AND ENERGY COMMENTS 8 1 2 POWER SPECTRAL DENSITY SPECTRUM ANALYZERS 8 2 CIRCUIT NOISE 8 2 1 CALCULATING AND MODELING CIRCUIT NOISE INPUT-REFERRED NOISE I NOISE EQUIVALENT BANDWIDTH INPUT-REFERRED NOISE IN CASCADED AMPLIFIERS CALCULATING VONOISE,RMS FROM A SPECTRUM: A SUMMARY 8 2 2 THERMAL NOISE 8 2 3 SIGNAL-TO-NOISE RATIO INPUT-REFERRED NOISE II NOISE FIGURE AN IMPORTANT LIMITATION OF THE NOISE FIGURE OPTIMUM SOURCE RESISTANCE SIMULATING NOISELESS RESISTORS NOISE TEMPERATURE AVERAGING WHITE NOISE 8 2 4 SHOT NOISE 8 2 5 FLICKER NOISE 8 2 6 OTHER NOISE SOURCES RANDOM TELEGRAPH SIGNAL NOISE EXCESS NOISE (FLICKER NOISE) AVALANCHE NOISE 8 3 DISCUSSION 8 3 1 CORRELATION CORRELATION OF INPUT-REFERRED NOISE SOURCES COMPLEX INPUT IMPEDANCE 8 3 2 NOISE AND FEEDBACK OP-AMP NOISE MODELING 8 3 3 SOME FINAL NOTES CONCERNING NOTATION CHAPTER 9 MODELS FOR ANALOG DESIGN 9 1 LONG-CHANNEL MOSFETS 9 1 1 THE SQUARE-LAW EQUATIONS PMOS SQUARE-LAW EQUATIONS QUALITATIVE DISCUSSION THE TRIODE REGION THE CUTOFF AND SUBTHRESHOLD REGIONS 9 1 2 SMALL SIGNAL MODELS TRANSCONDUCTANCE BODY EFFECT TRANSCONDUCTANCE, GMB OUTPUT RESISTANCE MOSFET TRANSITION FREQUENCY, FT GENERAL DEVICE SIZES FOR ANALOG DESIGN SUBTHRESHOLD GM AND VTHN 9 1 3 TEMPERATURE EFFECTS THRESHOLD VARIATION AND TEMPERATURE MOBILITY VARIATION WITH TEMPERATURE DRAIN CURRENT CHANGE WITH TEMPERATURE 9 2 SHORT-CHANNEL MOSFETS 9 2 1 GENERAL DESIGN (A STARTING POINT) FORWARD TRANSCONDUCTANCE TRANSITION FREQUENCY 9 2 2 SPECIFIC DESIGN (A DISCUSSION) 9 3 MOSFET NOISE MODELING DRAIN CURRENT NOISE MODEL CHAPTER 10 MODELS FOR DIGITAL DESIGN MILLER CAPACITANCE 10 1 THE DIGITAL MOSFET MODEL EFFECTIVE SWITCHING RESISTANCE SHORT-CHANNEL MOSFET EFFECTIVE SWITCHING RESISTANCE 10 1 1 CAPACITIVE EFFECTS 10 1 2 PROCESS CHARACTERISTIC TIME CONSTANT 10 1 3 DELAY AND TRANSITION TIMES 10 1 4 GENERAL DIGITAL DESIGN 10 2 THE MOSFET PASS GATE THE PMOS PASS GATE 10 2 1 DELAY THROUGH A PASS GATE THE TRANSMISSION GATE (THE TG) 10 2 2 DELAY THROUGH SERIES-CONNECTED PGS 10 3 A FINAL COMMENT CONCERNING MEASUREMENTS CHAPTER 11 THE INVERTER 11 1 DC CHARACTERISTICS NOISE MARGINS INVERTER SWITCHING POINT IDEAL INVERTER VTC AND NOISE MARGINS 11 2 SWITCHING CHARACTERISTICS THE RING OSCILLATOR DYNAMIC POWER DISSIPATION 11 3 LAYOUT OF THE INVERTER LATCH-UP 11 4 SIZING FOR LARGE CAPACITIVE LOADS BUFFER TOPOLOGY DISTRIBUTED DRIVERS DRIVING LONG LINES 11 5 OTHER INVERTER CONFIGURATIONS NMOS-ONLY OUTPUT DRIVERS INVERTERS WITH TRI-STATE OUTPUTS ADDITIONAL EXAMPLES CHAPTER 12 STATIC LOGIC GATES 12 1 DC CHARACTERISTICS OF THE NAND AND NOR GATES 12 1 1 DC CHARACTERISTICS OF THE NAND GATE 12 1 2 DC CHARACTERISTICS OF THE NOR GATE A PRACTICAL NOTE CONCERNING VSP AND PASS GATES 12 2 LAYOUT OF THE NAND AND NOR GATES 12 3 SWITCHING CHARACTERISTICS PARALLEL CONNECTION OF MOSFETS SERIES CONNECTION OF MOSFETS 12 3 1 NAND GATE QUICK ESTIMATE OF DELAYS 12 3 2 NUMBER OF INPUTS 12 4 COMPLEX CMOS LOGIC GATES CASCODE VOLTAGE SWITCH LOGIC DIFFERENTIAL SPLIT-LEVEL LOGIC TRI-STATE OUTPUTS CHAPTER 13 CLOCKED CIRCUITS 13 1 THE CMOS TG SERIES CONNECTION OF TGS 13 2 APPLICATIONS OF THE TRANSMISSION GATE PATH SELECTOR STATIC CIRCUITS 13 3 LATCHES AND FLIP-FLOPS BASIC LATCHES AN ARBITER FLIP-FLOPS AND FLOW-THROUGH LATCHES AN EDGE-TRIGGERED D-FF FLIP-FLOP TIMING 13 4 EXAMPLES CHAPTER 14 DYNAMIC LOGIC GATES 14 1 FUNDAMENTALS OF DYNAMIC LOGIC 14 1 1 CHARGE LEAKAGE 14 1 2 SIMULATING DYNAMIC CIRCUITS 14 1 3 NONOVERLAPPING CLOCK GENERATION 14 1 4 CMOS TG IN DYNAMIC CIRCUITS 14 2 CLOCKED CMOS LOGIC CLOCKED CMOS LATCH PE LOGIC DOMINO LOGIC NP LOGIC (ZIPPER LOGIC) PIPELINING CHAPTER 15 CMOS LAYOUT EXAMPLES 15 1 CHIP LAYOUT REGULARITY STANDARD CELL EXAMPLES POWER AND GROUND CONSIDERATIONS AN ADDER EXAMPLE A 4-TO-1 MUX/DEMUX 15 2 LAYOUT STEPS BY DEAN MORIARTY PLANNING AND STICK DIAGRAMS DEVICE PLACEMENT POLISH STANDARD CELLS VERSUS FULL-CUSTOM LAYOUT CHAPTER 16 MEMORY CIRCUITS 16 1 ARRAY ARCHITECTURES 16 1 1 SENSING BASICS NMOS SENSE AMPLIFIER (NSA) THE OPEN ARRAY ARCHITECTURE PMOS SENSE AMPLIFIER (PSA) REFRESH OPERATION 16 1 2 THE FOLDED ARRAY LAYOUT OF THE DRAM MEMORY BIT (MBIT) 16 1 3 CHIP ORGANIZATION 16 2 PERIPHERAL CIRCUITS 16 2 1 SENSE AMPLIFIER DESIGN KICKBACK NOISE AND CLOCK FEEDTHROUGH MEMORY CURRENT DRAW CONTENTION CURRENT (SWITCHING CURRENT) REMOVING SENSE AMPLIFIER MEMORY CREATING AN IMBALANCE AND REDUCING KICKBACK NOISE INCREASING THE INPUT RANGE SIMULATION EXAMPLES 16 2 2 ROW/COLUMN DECODERS GLOBAL AND LOCAL DECODERS REDUCING DECODER LAYOUT AREA 16 2 3 ROW DRIVERS 16 3 MEMORY CELLS 16 3 1 THE SRAM CELL 16 3 2 READ-ONLY MEMORY (ROM) 16 3 3 FLOATING GATE MEMORY THE THRESHOLD VOLTAGE ERASABLE PROGRAMMABLE READ-ONLY MEMORY TWO IMPORTANT NOTES FLASH MEMORY CHAPTER 17 SENSING USING MODULATION 17 1 QUALITATIVE DISCUSSION 17 1 1 EXAMPLES OF DSM THE COUNTER CUP SIZE ANOTHER EXAMPLE 17 1 2 USING DSM FOR SENSING IN FLASH MEMORY THE BASIC IDEA THE FEEDBACK SIGNAL INCOMPLETE SETTLING 17 2 SENSING RESISTIVE MEMORY THE BIT LINE VOLTAGE ADDING AN OFFSET TO THE COMPARATOR SCHEMATIC AND DESIGN VALUES A COUPLE OF COMMENTS 17 3 SENSING IN CMOS IMAGERS RESETTING THE PIXEL THE INTENSITY LEVEL SAMPLING THE REFERENCE AND INTENSITY SIGNALS NOISE ISSUES SUBTRACTING VR FROM VS SENSING CIRCUIT MISMATCHES CHAPTER 18 SPECIAL PURPOSE CMOS CIRCUITS 18 1 THE SCHMITT TRIGGER 18 1 1 DESIGN OF THE SCHMITT TRIGGER SWITCHING CHARACTERISTICS 18 1 2 APPLICATIONS OF THE SCHMITT TRIGGER 18 2 MULTIVIBRATOR CIRCUITS 18 2 1 THE MONOSTABLE MULTIVIBRATOR 18 2 2 THE ASTABLE MULTIVIBRATOR 18 3 INPUT BUFFERS 18 3 1 BASIC CIRCUITS SKEW IN LOGIC GATES 18 3 2 DIFFERENTIAL CIRCUITS TRANSIENT RESPONSE 18 3 3 DC REFERENCE 18 3 4 REDUCING BUFFER INPUT RESISTANCE 18 4 CHARGE PUMPS (VOLTAGE GENERATORS) NEGATIVE VOLTAGES USING MOSFETS FOR THE CAPACITORS 18 4 1 INCREASING THE OUTPUT VOLTAGE 18 4 2 GENERATING HIGHER VOLTAGES: THE DICKSON CHARGE PUMP CLOCK DRIVER WITH A PUMPED OUTPUT VOLTAGE NMOS CLOCK DRIVER 18 4 3 EXAMPLE CHAPTER 19 DIGITAL PHASE-LOCKED LOOPS 19 1 THE PHASE DETECTOR 19 1 1 THE XOR PHASE DETECTOR 19 1 2 THE PHASE FREQUENCY DETECTOR 19 2 THE VOLTAGE-CONTROLLED OSCILLATOR 19 2 1 THE CURRENT-STARVED VCO LINEARIZING THE VCO’S GAIN 19 2 2 SOURCE-COUPLED VCOS 19 3 THE LOOP FILTER 19 3 1 XOR DPLL ACTIVE-PI LOOP FILTER 19 3 2 PFD DPLL TRI-STATE OUTPUT IMPLEMENTING THE PFD IN CMOS PFD WITH A CHARGE PUMP OUTPUT PRACTICAL IMPLEMENTATION OF THE CHARGE PUMP DISCUSSION 19 4 SYSTEM CONCERNS 19 4 1 CLOCK RECOVERY FROM NRZ DATA THE HOGGE PHASE DETECTOR JITTER 19 5 DELAY-LOCKED LOOPS DELAY ELEMENTS PRACTICAL VCO AND VCDL DESIGN 19 6 SOME EXAMPLES 19 6 1 A 2 GHZ DLL 19 6 2 A 1 GBIT/S CLOCK-RECOVERY CIRCUIT CHAPTER 20 CURRENT MIRRORS 20 1 THE BASIC CURRENT MIRROR 20 1 1 LONG-CHANNEL DESIGN 20 1 2 MATCHING CURRENTS IN THE MIRROR THRESHOLD VOLTAGE MISMATCH TRANSCONDUCTANCE PARAMETER MISMATCH DRAIN-TO-SOURCE VOLTAGE AND LAMBDA LAYOUT TECHNIQUES TO IMPROVE MATCHING LAYOUT OF THE MIRROR WITH DIFFERENT WIDTHS 20 1 3 BIASING THE CURRENT MIRROR USING A MOSFET-ONLY REFERENCE CIRCUIT SUPPLY INDEPENDENT BIASING 20 1 4 SHORT-CHANNEL DESIGN 20 1 5 TEMPERATURE BEHAVIOR RESISTOR-MOSFET REFERENCE CIRCUIT MOSFET-ONLY REFERENCE CIRCUIT TEMPERATURE BEHAVIOR OF THE BETA-MULTIPLIER VOLTAGE REFERENCE USING THE BETA-MULTIPLIER 20 1 6 BIASING IN THE SUBTHRESHOLD REGION 20 2 CASCODING THE CURRENT MIRROR 20 2 1 THE SIMPLE CASCODE DC OPERATION CASCODE OUTPUT RESISTANCE 20 2 2 LOW-VOLTAGE (WIDE-SWING) CASCODE AN IMPORTANT PRACTICAL NOTE LAYOUT CONCERNS 20 2 3 WIDE-SWING, SHORT-CHANNEL DESIGN 20 2 4 REGULATED DRAIN CURRENT MIRROR 20 3 BIASING CIRCUITS 20 3 1 LONG-CHANNEL BIASING CIRCUITS BASIC CASCODE BIASING THE FOLDED-CASCODE STRUCTURE 20 3 2 SHORT-CHANNEL BIASING CIRCUITS FLOATING CURRENT SOURCES 20 3 3 A FINAL COMMENT CHAPTER 21 AMPLIFIERS 21 1 GATE-DRAIN CONNECTED LOADS 21 1 1 COMMON-SOURCE (CS) AMPLIFIERS MILLER’S THEOREM FREQUENCY RESPONSE THE RIGHT-HAND PLANE ZERO A COMMON-SOURCE CURRENT AMPLIFIER COMMON-SOURCE AMPLIFIER WITH SOURCE DEGENERATION NOISE PERFORMANCE OF THE CS AMPLIFIER WITH GATE-DRAIN LOAD 21 1 2 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) 21 1 3 COMMON GATE AMPLIFIER 21 2 CURRENT SOURCE LOADS 21 2 1 COMMON-SOURCE AMPLIFIER CLASS A OPERATION SMALL-SIGNAL GAIN OPEN CIRCUIT GAIN HIGH-IMPEDANCE AND LOW-IMPEDANCE NODES POLE SPLITTING POLE SPLITTING SUMMARY CANCELING THE RHP ZERO NOISE PERFORMANCE OF THE CS AMPLIFIER WITH CURRENT SOURCE LOAD 21 2 2 THE CASCODE AMPLIFIER NOISE PERFORMANCE OF THE CASCODE AMPLIFIER OPERATION AS A TRANSIMPEDANCE AMPLIFIER 21 2 3 THE COMMON-GATE AMPLIFIER 21 2 4 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) BODY EFFECT AND GAIN LEVEL SHIFTING INPUT CAPACITANCE NOISE PERFORMANCE OF THE SF AMPLIFIER FREQUENCY BEHAVIOR SF AS AN OUTPUT BUFFER A CLASS AB OUTPUT BUFFER USING SFS 21 3 THE PUSH-PULL AMPLIFIER 21 3 1 DC OPERATION AND BIASING POWER CONVERSION EFFICIENCY 21 3 2 SMALL-SIGNAL ANALYSIS 21 3 3 DISTORTION MODELING DISTORTION WITH SPICE CHAPTER 22 DIFFERENTIAL AMPLIFIERS 22 1 THE SOURCE-COUPLED PAIR 22 1 1 DC OPERATION MAXIMUM AND MINIMUM DIFFERENTIAL INPUT VOLTAGE MAXIMUM AND MINIMUM COMMON-MODE INPUT VOLTAGE CURRENT MIRROR LOAD BIASING FROM THE CURRENT MIRROR LOAD MINIMUM POWER SUPPLY VOLTAGE 22 1 2 AC OPERATION AC GAIN WITH A CURRENT MIRROR LOAD 22 1 3 COMMON-MODE REJECTION RATIO INPUT-REFERRED OFFSET FROM FINITE CMRR 22 1 4 MATCHING CONSIDERATIONS INPUT-REFERRED OFFSET WITH A CURRENT MIRROR LOAD 22 1 5 NOISE PERFORMANCE 22 1 6 SLEW-RATE LIMITATIONS 22 2 THE SOURCE CROSS-COUPLED PAIR OPERATION OF THE DIFF-AMP INPUT SIGNAL RANGE 22 2 1 CURRENT SOURCE LOAD 22 3 CASCODE LOADS (THE TELESCOPIC DIFF-AMP) 22 4 WIDE-SWING DIFFERENTIAL AMPLIFIERS 22 4 1 CURRENT DIFFERENTIAL AMPLIFIER 22 4 2 CONSTANT TRANSCONDUCTANCE DIFF-AMP CHAPTER 23 VOLTAGE REFERENCES 23 1 MOSFET-RESISTOR VOLTAGE REFERENCES 23 1 1 THE RESISTOR-MOSFET DIVIDER 23 1 2 THE MOSFET-ONLY VOLTAGE DIVIDER 23 1 3 SELF-BIASED VOLTAGE REFERENCES FORCING THE SAME CURRENT THROUGH EACH SIDE OF THE REFERENCE AN ALTERNATE TOPOLOGY 23 2 PARASITIC DIODE-BASED REFERENCES DIODE BEHAVIOR THE BANDGAP ENERGY OF SILICON LOWER VOLTAGE REFERENCE DESIGN 23 2 1 LONG-CHANNEL BGR DESIGN DIODE-REFERENCED SELF-BIASING (CTAT) THERMAL VOLTAGE-REFERENCED SELF-BIASING (PTAT) BANDGAP REFERENCE DESIGN ALTERNATIVE BGR TOPOLOGIES 23 2 2 SHORT-CHANNEL BGR DESIGN THE ADDED AMPLIFIER LOWER VOLTAGE OPERATION CHAPTER 24 OPERATIONAL AMPLIFIERS I 24 1 THE TWO-STAGE OP-AMP LOW-FREQUENCY, OPEN LOOP GAIN, AOLDC INPUT COMMON-MODE RANGE POWER DISSIPATION OUTPUT SWING AND CURRENT SOURCE/SINKING CAPABILITY OFFSETS COMPENSATING THE OP-AMP GAIN AND PHASE MARGINS REMOVING THE ZERO COMPENSATION FOR HIGH-SPEED OPERATION SLEW-RATE LIMITATIONS COMMON-MODE REJECTION RATIO (CMRR) POWER SUPPLY REJECTION RATIO (PSRR) INCREASING THE INPUT COMMON-MODE VOLTAGE RANGE ESTIMATING BANDWIDTH IN OP-AMPS CIRCUITS 24 2 AN OP-AMP WITH OUTPUT BUFFER 24 3 THE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) UNITY-GAIN FREQUENCY, FUN INCREASING THE OTA OUTPUT RESISTANCE OTA WITH AN OUTPUT BUFFER (AN OP-AMP) THE FOLDED-CASCODE OTA AND OP-AMP 24 4 GAIN-ENHANCEMENT BANDWIDTH OF THE ADDED GE AMPLIFIERS COMPENSATING THE ADDED GE AMPLIFIERS 24 5 SOME EXAMPLES AND DISCUSSIONS A VOLTAGE REGULATOR BAD OUTPUT STAGE DESIGN THREE-STAGE OP-AMP DESIGN CHAPTER 25 DYNAMIC ANALOG CIRCUITS 25 1 THE MOSFET SWITCH CHARGE INJECTION CAPACITIVE FEEDTHROUGH REDUCTION OF CHARGE INJECTION AND CLOCK FEEDTHROUGH KT/C NOISE 25 1 1 SAMPLE-AND-HOLD CIRCUITS 25 2 FULLY-DIFFERENTIAL CIRCUITS GAIN COMMON-MODE FEEDBACK COUPLED NOISE REJECTION OTHER BENEFITS OF FULLY-DIFFERENTIAL OP-AMPS 25 2 1 A FULLY-DIFFERENTIAL SAMPLE-AND-HOLD CONNECTING THE INPUTS TO THE BOTTOM (POLY1) PLATE BOTTOM PLATE SAMPLING SPICE SIMULATION 25 3 SWITCHED-CAPACITOR CIRCUITS 25 3 1 SWITCHED-CAPACITOR INTEGRATOR PARASITIC INSENSITIVE OTHER INTEGRATOR CONFIGURATIONS EXACT FREQUENCY RESPONSE OF A SWITCHED-CAPACITOR INTEGRATOR CAPACITOR LAYOUT OP-AMP SETTLING TIME 25 4 CIRCUITS REDUCING OFFSET VOLTAGE OF AN OP-AMP DYNAMIC COMPARATOR DYNAMIC CURRENT MIRRORS DYNAMIC AMPLIFIERS CHAPTER 26 OPERATIONAL AMPLIFIERS II 26 1 BIASING FOR POWER AND SPEED 26 1 1 DEVICE CHARACTERISTICS 26 1 2 BIASING CIRCUIT LAYOUT OF DIFFERENTIAL OP-AMPS SELF-BIASED REFERENCE 26 2 BASIC CONCEPTS MODELING OFFSET A DIFF-AMP A SINGLE BIAS INPUT DIFF-AMP THE DIFF-AMP’S TAIL CURRENT SOURCE USING A CMFB AMPLIFIER COMPENSATING THE CMFB LOOP EXTENDING THE CMFB AMPLIFIER INPUT RANGE DYNAMIC CMFB 26 3 BASIC OP-AMP DESIGN THE DIFFERENTIAL AMPLIFIER ADDING A SECOND STAGE (MAKING AN OP-AMP) ADDING CMFB CMFB AMPLIFIER THE TWO-STAGE OP-AMP WITH CMFB ORIGIN OF THE PROBLEM USING MOSFETS OPERATING IN THE TRIODE REGION START-UP PROBLEMS LOWERING INPUT CAPACITANCE MAKING THE OP-AMP MORE PRACTICAL INCREASING THE OP-AMP’S OPEN-LOOP GAIN OP-AMP OFFSET EFFECTS ON OUTPUTS SINGLE-ENDED TO DIFFERENTIAL CONVERSION CMFB SETTLING TIME CMFB IN THE OUTPUT BUFFER (FIG 26 43) OR THE DIFF-AMP (FIG 26 40)? 26 4 OP-AMP DESIGN USING SWITCHED-CAPACITOR CMFB CLOCK SIGNALS SWITCHED-CAPACITOR CMFB THE OP-AMP’S FIRST STAGE THE OUTPUT BUFFER AN APPLICATION OF THE OP-AMP A FINAL NOTE CONCERNING BIASING CHAPTER 27 NONLINEAR ANALOG CIRCUITS 27 1 BASIC CMOS COMPARATOR DESIGN PREAMPLIFICATION DECISION CIRCUIT OUTPUT BUFFER 27 1 1 CHARACTERIZING THE COMPARATOR COMPARATOR DC PERFORMANCE PROPAGATION DELAY MINIMUM INPUT SLEW RATE 27 1 2 CLOCKED COMPARATORS 27 1 3 INPUT BUFFERS REVISITED 27 2 ADAPTIVE BIASING 27 3 ANALOG MULTIPLIERS 27 3 1 THE MULTIPLYING QUAD SIMULATING THE OPERATION OF THE MULTIPLIER 27 3 2 MULTIPLIER DESIGN USING SQUARING CIRCUITS CHAPTER 28 DATA CONVERTER FUNDAMENTALS BY HARRY LI 28 1 ANALOG VERSUS DISCRETE TIME SIGNALS 28 2 CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 28 3 SAMPLE-AND-HOLD (S/H) CHARACTERISTICS SAMPLE MODE HOLD MODE APERTURE ERROR 28 4 DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY OFFSET GAIN ERROR LATENCY SIGNAL-TO-NOISE RATIO (SNR) DYNAMIC RANGE 28 5 ANALOG-TO-DIGITAL CONVERTER (ADC) SPECIFICATIONS QUANTIZATION ERROR MISSING CODES OFFSET AND GAIN ERROR ALIASING SIGNAL-TO-NOISE RATIO 28 6 MIXED-SIGNAL LAYOUT ISSUES FLOORPLANNING POWER SUPPLY AND GROUND ISSUES FULLY DIFFERENTIAL DESIGN SHIELDING OTHER INTERCONNECT CONSIDERATIONS CHAPTER 29 DATA CONVERTER ARCHITECTURES BY HARRY LI 29 1 DAC ARCHITECTURES 29 1 1 DIGITAL INPUT CODE 29 1 2 RESISTOR STRING MISMATCH ERRORS RELATED TO THE RESISTOR-STRING DAC INTEGRAL NONLINEARITY OF THE RESISTOR-STRING DAC DIFFERENTIAL NONLINEARITY OF THE WORST-CASE RESISTOR- STRING DAC 29 1 3 R-2R LADDER NETWORKS 29 1 4 CURRENT STEERING MISMATCH ERRORS RELATED TO CURRENT-STEERING DACS 29 1 5 CHARGE-SCALING DACS LAYOUT CONSIDERATIONS FOR A BINARY-WEIGHTED CAPACITOR ARRAY THE SPLIT ARRAY 29 1 6 CYCLIC DAC 29 1 7 PIPELINE DAC 29 2 ADC ARCHITECTURES 29 2 1 FLASH ACCURACY ISSUES FOR THE FLASH ADC 29 2 2 THE TWO-STEP FLASH ADC ACCURACY ISSUES RELATED TO THE TWO-STEP FLASH CONVERTER ACCURACY ISSUES RELATED TO OPERATIONAL AMPLIFIERS 29 2 3 THE PIPELINE ADC ACCURACY ISSUES RELATED TO THE PIPELINE CONVERTER 29 2 4 INTEGRATING ADCS SINGLE-SLOPE ARCHITECTURE ACCURACY ISSUES RELATED TO THE SINGLE-SLOPE ADC DUAL-SLOPE ARCHITECTURE ACCURACY ISSUES RELATED TO THE DUAL-SLOPE ADC 29 2 5 THE SUCCESSIVE APPROXIMATION ADC THE CHARGE-REDISTRIBUTION SUCCESSIVE APPROXIMATION ADC ACCURACY ISSUES RELATED TO THE CHARGE- REDISTRIBUTION,SUCCESSIVE-APROXIMATION ADC 29 2 6 THE OVERSAMPLING ADC DIFFERENCES IN NYQUIST RATE AND OVERSAMPLED ADCS THE FIRST-ORDER MODULATOR THE HIGHER ORDER MODULATORS CHAPTER 30 IMPLEMENTING DATA CONVERTERS 30 1 R-2R TOPOLOGIES FOR DACS 30 1 1 THE CURRENT-MODE R-2R DAC 30 1 2 THE VOLTAGE-MODE R-2R DAC 30 1 3 A WIDE-SWING CURRENT-MODE R-2R DAC DNL ANALYSIS INL ANALYSIS SWITCHES EXPERIMENTAL RESULTS IMPROVING DNL (SEGMENTATION) TRIMMING DAC OFFSET TRIMMING DAC GAIN IMPROVING INL BY CALIBRATION 30 1 4 TOPOLOGIES WITHOUT AN OP-AMP THE VOLTAGE-MODE DAC TWO IMPORTANT NOTES CONCERNING GLITCHES THE CURRENT-MODE (CURRENT STEERING) DAC 30 2 OP-AMPS IN DATA CONVERTERS GAIN BANDWIDTH PRODUCT OF THE NONINVERTING OP-AMP TOPOLOGY GAIN BANDWIDTH PRODUCT OF THE INVERTING OP-AMP TOPOLOGY 30 2 1 OP-AMP GAIN 30 2 2 OP-AMP UNITY GAIN FREQUENCY 30 2 3 OP-AMP OFFSET ADDING AN AUXILIARY INPUT PORT 30 3 IMPLEMENTING ADCS 30 3 1 IMPLEMENTING THE S/H A SINGLE-ENDED TO DIFFERENTIAL OUTPUT S/H 30 3 2 THE CYCLIC ADC COMPARATOR PLACEMENT IMPLEMENTING SUBTRACTION IN THE S/H UNDERSTANDING OUTPUT SWING 30 3 3 THE PIPELINE ADC USING 1 5 BITS/STAGE CAPACITOR ERROR AVERAGING CLOCK GENERATION OFFSETS AND ALTERNATIVE DESIGN TOPOLOGIES LAYOUT OF PIPELINED ADCS CHAPTER 31 FEEDBACK AMPLIFIERS WITH HARRY LI 31 1 THE FEEDBACK EQUATION 31 2 PROPERTIES OF NEGATIVE FEEDBACK ON AMPLIFIER DESIGN 31 2 1 GAIN DESENSITIVITY 31 2 2 BANDWIDTH EXTENSION 31 2 3 REDUCTION IN NONLINEAR DISTORTION 31 2 4 INPUT AND OUTPUT IMPEDANCE CONTROL 31 3 RECOGNIZING FEEDBACK TOPOLOGIES 31 3 1 INPUT MIXING 31 3 2 OUTPUT SAMPLING 31 3 3 THE FEEDBACK NETWORK AN IMPORTANT ASSUMPTION COUNTING INVERSIONS AROUND THE LOOP EXAMPLES OF RECOGNIZING FEEDBACK TOPOLOGIES 31 3 4 CALCULATING OPEN-LOOP PARAMETERS 31 3 5 CALCULATING CLOSED-LOOP PARAMETERS 31 4 THE VOLTAGE AMP (SERIES-SHUNT FEEDBACK) 31 5 THE TRANSIMPEDANCE AMP (SHUNT-SHUNT FEEDBACK) 31 5 1 SIMPLE FEEDBACK USING A GATE-DRAIN RESISTOR 31 6 THE TRANSCONDUCTANCE AMP (SERIES-SERIES FEEDBACK) 31 7 THE CURRENT AMPLIFIER (SHUNT-SERIES FEEDBACK) 31 8 STABILITY 31 8 1 THE RETURN RATIO 31 9 DESIGN EXAMPLES 31 9 1 VOLTAGE AMPLIFIERS AMPLIFIERS WITH GAIN 31 9 2 A TRANSIMPEDANCE AMPLIFIER CHAPTER 32 HYSTERETIC POWER CONVERTERS 32 1 A REVIEW OF POWER AND ENERGY BASICS AN ANALOGY 32 1 1 ENERGY STORAGE IN INDUCTORS AND CAPACITORS ENERGY STORAGE IN AN INDUCTOR ENERGY STORAGE IN A CAPACITOR 32 1 2 ENERGY USE IN TRANSMITTING DATA 32 1 3 SELECTION AND USE OF SWITCHES USING AN NMOS PULL-UP EFFECTIVE DIGITAL RESISTANCE, A COMMENT DRIVER OPTIMIZATION HIGHER VOLTAGE SWITCHES 32 2 SWITCHING POWER SUPPLIES: SOME EXAMPLES 32 2 1 THE BUCK SPS SELECTING THE INDUCTOR SELECTING THE CAPACITOR POWER SUPPLY EFFICIENCY 32 2 2 THE BOOST SPS 32 2 3 THE FLYBACK SPS QUICK REVIEW OF TRANSFORMERS OPERATION OF THE FLYBACK SPS 32 2 4 PULSE WIDTH MODULATION: A CONTROL LOOP EXAMPLE BUCK SPS CONTROL LOOP BOOST SPS CONTROL LOOP FLYBACK SPS CONTROL LOOP EFFECTIVE SERIES RESISTANCE SOME COMMENTS 32 3 HYSTERETIC CONTROL 32 3 1 TOPOLOGIES 32 3 2 EXAMPLES BUCK HPS CONTROL LOOP BOOST HPS CONTROL LOOP FLYBACK HPS CONTROL LOOP SOME FINAL COMMENTS