TRANSISTOR ELECTRONICS

By EMILY SANCHEZ

TABLE OF CONTENTS CHAPTER 1 INTRODUCTION 1 CHAPTER 2 DEVICE MODELING OVERVIEW 15 CHAPTER 3 THEORY OF HOMOJUNCTION BIPOLAR TRANSISTORS 55 CHAPTER 4 ADVANCED THEORY 157 CHAPTER 5 GEOMETRY LAYOUT SCALING 279 CHAPTER 6 TEMPERATURE EFFECTS 409 CHAPTER 7 COMPACT NOISE MODELING 449 CHAPTER 8 HICUM LEVEL2 481 CHAPTER 9 PARAMETER DETERMINATION FOR HICUM L2 557 CHAPTER 10 MODEL HIERARCHY 609 CHAPTER 1 INTRODUCTION ALTHOUGH CMOS HAS BEEN THE MAINSTREAM TECHNOLOGY OVER MORE THAN THE PAST TWO DECADES EVEN TODAY SILICON BASED BIPOLAR TRANSISTORS ARE STILL LEADING THEIR FIELD EFFECT COUNTERPARTS IN TERMS OF OPERATING SPEED FOR BOTH DEVICES AND CIRCUITS1 THIS SPEED ADVANTAGE SEEMED TO FADE IN THE LATE EIGHTIES WHEN STAND ALONE BIPOLAR TECHNOLOGY LOST GROUND TO CMOS DUE TO THE USE OF DEPRECIATED AND OLD FABRICATION TOOLS BUT BECAME OBVIOUS AGAIN BY THE MID NINETIES WHEN THE SILICON GERMANIUM SIGE HETEROJUNC TION BIPOLAR TRANSISTOR HBT WAS DEVELOPED AND SUBSEQUENTLY ALSO INTE GRATED INTO A CMOS BASELINE PROCESS SINCE THEN THE RESULTING BICMOS TECHNOLOGY HAS GAINED TREMENDOUS SUCCESS AS CAN BE OBSERVED FROM THE NUMBER OF COMMERCIAL FABRICATION FACILITIES WHICH HAS GROWN WITHIN THE PAST DECADE FROM ONE IN THE MID NINETIES TO OVER 30 E G 1 IN ADDITION THERE ARE NUMEROUS 20 COMPANIES WORLDWIDE WITH FACILITIES FOR FABRI CATING HBTS IN III V MATERIALS SUCH AS GAAS INP AND GAN FINALLY BOTH HBTS AND SILICON HOMOJUNCTION BIPOLAR TRANSISTORS BJTS STILL CAPTURE A QUITE SIZEABLE MARKET FOR DISCRETE LINEAR ANALOG APPLICATIONS WHILE SILICON CARBIDE HBTS HAVE POSITIONED THEMSELVES QUITE WELL FOR HIGH VOLTAGE AND HIGH TEMPERATURE OPERATION IN THE AUTOMOTIVE AND HIGH POWER MARKET IN FACT MEASURED JUST BY VOLUME THE DISCRETE MARKET STILL HAS QUITE A SUBSTANTIAL SHARE IN SHIPPED ITEMS ITS 2008 REVENUE IS ABOUT 7 OF THE 273 BILLION SEMICONDUCTOR INDUSTRY WITH AN AVERAGE ANNUAL GROWTH RATE 1 ASSUMING BOTH TRANSISTOR TYPES ARE REALIZED IN THE SAME MATERIAL SYSTEM AND LITHOGRAPHY NODE I E THE SAME CRITICAL DIMENSIONS FOR MORE DETAILS AND DATA REGARDING THIS COMPARISON SEE CHAPTER ON FUTURE TRENDS 1 OF 5 OVERALL THE ANALOG INTEGRATED CIRCUITS ICS AND DISCRETE MARKET TO GETHER CONSTITUTE 21 PERCENT INTERESTINGLY OVER THE NEXT 5 YEARS THE ANALOG IC MARKET IS EXPECTED TO HAVE AN AVERAGE ANNUAL GROWTH RATE OF 12 AND TO OUTPERFORM THE EXPECTED GROWTH RATES FOR BOTH THE DIGITAL MARKET 6 AND THE GLOBAL MARKET 7 2 DUE TO THEIR SUPERIOR ANALOG HIGH FREQUENCY HF CHARACTERISTICS AND PERFORMANCE E G 3 BIPOLAR TRANSISTORS HAVE MAINTAINED A STRONG FOOT HOLD IN CORRESPONDING APPLICATION AREAS SUCH AS COMMUNICATIONS AUTOMO TIVE MEASUREMENT EQUIPMENT AND POWER CONTROL IN FACT THE LINEAR AND DISCRETE MARKET IS STILL DOMINATED BY BIPOLAR TECHNOLOGY THE PERFORMANCE AND FUNCTIONALITY OF INTEGRATED CIRCUITS AND SYSTEMS HAVE BENEFITTED SIGNIF ICANTLY FROM THE CAPABILITY OF BICMOS TECHNOLOGY WHICH OFTEN OFFERS AN EARLY AND COST EFFICIENT INTRODUCTION OF HF HIGH SPEED PRODUCTS IT IS WORTH NOTING THAT THE USE OF GE IS BENEFICIAL TO THE PERFORMANCE OF SIGE HBTS TO A MUCH HIGHER EXTENT THAN IN STRAINED SIGE MOSFETS WHILE IN BOTH TRAN SISTOR TYPES THE STRAIN CAUSED BY INTRODUCING GE INCREASES THE MOBILITY THE VERTICAL LAYER STRUCTURE IN HBTS ALSO ALLOWS TO CREATE AIDING FIELDS AND TRADE OFF E G CURRENT GAIN VERSUS SPEED THROUGH ENERGY GAP BANDGAP2 ENGI NEERING HENCE IT DOES NOT COME AT A SURPRISE THAT SIGE BICMOS TECHNOL OGY HAS FOUND NUMEROUS APPLICATIONS CF 1 AND THE CHAPTER ON FUTURE TRENDS IN THIS BOOK AS A CONSEQUENCE SIGE HBTS ARE THE MAIN TOPIC OF THIS BOOK ALTHOUGH THEIR THEORETICAL TREATMENT OF COURSE IS BUILT ON THE GE NERIC FUNDAMENTALS APPLYING ALSO TO BJTS CIRCUIT DESIGN AND OPTIMIZATION TODAY ARE HEAVILY BASED ON SIMULATION IN OTHER WORDS A CIRCUIT DESIGNER GENERALLY OBSERVES THE FEATURES OF A SEMI CONDUCTOR PROCESS TECHNOLOGY THROUGH A SO CALLED PROCESS DESIGN KIT PDK IN ORDER TO REFLECT REALITY AS MUCH AS POSSIBLE AND HENCE TO MINI MIZE DESIGN ITERATIONS AND COST THE PDK MUST CONTAIN VERY ACCURATE MOD ELS OF THE DEVICES FABRICATED IN THE UNDERLYING PROCESS ON THE OTHER HAND SUCH MODELS NEED TO BE SUFFICIENTLY SIMPLE FOR CIRCUIT SIMULATION IN TERMS OF COMPUTATIONAL EFFORT I E SIMULATION TIME IF ANALOG HF CIRCUITS WITH HUNDREDS OR UP TO MANY THOUSANDS OF DIFFERENT DEVICES HAVE TO BE SIMULAT 2 ALTHOUGH THE PHYSICALLY CORRECT EXPRESSION HERE IS ENERGY GAP THE DESIGNATION BANDGAP WILL BE USED IN THE BOOK SINCE IT HAS BEEN IN USE FOR MANY YEARS IN THE EXISTING ENGINEERING LITERATURE 2 ED IN TIME DOMAIN DEVICE MODELS THAT ARE SUITABLE FOR SUCH TASKS ARE GEN ERALLY KNOWN UNDER THE TERM COMPACT MODELS FOR A MORE DETAILED DEFINITION AND DISCUSSION SEE SEC 2 3 OPTIMIZING ANALOG HF CIRCUIT PERFORMANCE WITH RESPECT TO GIVEN SPECI FICATIONS IS GENERALLY ACHIEVED BY DEVICE SIZING E G 4 7 I E BY VARYING THE TRANSISTOR CONFIGURATION CONSISTING OF EMITTER DIMENSIONS AND CONTACT ARRANGEMENT FOR A GIVEN PROCESS THIS IS GENERALLY THE ONLY WAY TO ACHIEVE A PROPER TRADE OFF BETWEEN ELECTRICAL TRANSISTOR CHARACTERISTICS OR PARAME TERS THAT OFTEN COUNTERTREND EACH OTHER FIGURE 1 1 VISUALIZES THE DIFFICULTIES IN THE OPTIMIZATION TASK FOR TWO DIFFERENT TYPES OF CIRCUITS A LOW NOISE HF AMPLIFIER AND A CML CIRCUIT IN A LOW NOISE AMPLIFIER LNA THE LOWEST NOISE IS USUALLY OBTAINED CLOSE TO THE MINIMUM OF THE TRANSISTOR S MINI MUM NOISE FIGURE NFMIN HOWEVER NFMIN OCCURS AT A MUCH LOWER COLLEC TOR CURRENT DENSITY THAN THE PEAK OF THE TRANSIT FREQUENCY FT OR THE MAXIMUM OSCILLATION FREQUENCY FMAX WHICH INDICATE THE MAXIMUM SPEED OF THE DEVICE ITSELF HENCE IN AN LNA MINIMUM NOISE AND MAXIMUM OP ERATING FREQUENCY OR BANDWIDTH CAN GENERALLY NOT BE ACHIEVED SIMULTA NEOUSLY INSTEAD ONE HAS TO TRADE OFF ONE AGAINST THE OTHER BY VARYING THE COLLECTOR CURRENT DENSITY AT A GIVEN BIAS CURRENT IC THAT IS USUALLY DEFINED BY POWER DISSIPATION OR OTHER CONSTRAINTS THIS TRADE OFF IS PERFORMED BY VARYING THE EMITTER LENGTH 4 6 7 AND THUS THE ASSOCIATED EMITTER AREA AE IN DIGITAL CIRCUITS SUCH AS FREQUENCY DIVIDERS AND MULTIPLEXERS THE GOAL IS OFTEN TO MINIMIZE GATE DELAY D DEPENDING ON THE LOAD OR FAN OUT D USUALLY ASSUMES ITS MINIMUM BEYOND THE PEAK OF FT OR FMAX SEE FIG 1 1 SINCE MINIMUM D REQUIRES CURRENT SWITCH TRANSISTORS TO BE OP ERATED AT HIGH CURRENT DENSITIES ADDITIONAL JITTER MIGHT BE GENERATED 8 THEREFORE MINIMIZING BOTH D AND JITTER REQUIRES A CAREFUL SELECTION OF THE PROPER TRANSISTOR CONFIGURATION 4 9 FURTHERMORE DIFFERENT TRANSISTOR SIZ ES ARE GENERALLY ALSO NECESSARY IN BIAS CIRCUITS AS A CONSEQUENCE OF THE ABOVE DISCUSSION COMPACT MODELS NEED TO BE GEOMETRY SCALABLE WHICH MEANS THAT EVERY ELEMENT IN AN EQUIVALENT CIRCUIT EC HAS TO BE DESCRIBED AS A FUNCTION OF THE TRANSISTOR CONFIGURATION IN ADDITION DESIGN HOUSES DE MAND STATISTICAL MODELING AND DESIGN CAPABILITY FROM FOUNDRIES GOING EVEN FURTHER COMPETITION SOMETIMES FORCES FOUNDRIES TO RELEASE COMPACT MODELS THAT PREDICT THE TARGETED PERFORMANCE WITH SUFFICIENT ACCURACY WELL 3