EMBEDDED MICROPROCESSOR SYSTEMS
CONTENTS 1 INTRODUCTION APPLICATION AREAS AND EXAMPLES COMMON CHARACTERISTICS CHALLENGES IN EMBEDDED SYSTEM DESIGN DESIGN FLOWS STRUCTURE OF THIS BOOK ASSIGNMENTS 2 SPECIFICATIONS AND MODELING REQUIREMENTS MODELS OF COMPUTATION EARLY DESIGN PHASES USE CASES (MESSAGE) SEQUENCE CHARTS COMMUNICATING ?NITE STATE MACHINES (CFSMS) TIMED AUTOMATA STATECHARTS SYNCHRONOUS LANGUAGES SDL: A CASE OF MESSAGE PASSING DATA ?OW SCOPE KAHN PROCESS NETWORKS SYNCHRONOUS DATA ?OW SIMULINK PETRI NETS INTRODUCTION CONDITION/EVENT NETS PLACE/TRANSITION NETS PREDICATE/TRANSITION NETS EVALUATION DISCRETE EVENT BASED LANGUAGES VHDL SYSTEMC VERILOG AND SYSTEMVERILOG SPECC VON-NEUMANN LANGUAGES CSP ADA JAVA PEARL AND CHILL COMMUNICATION LIBRARIES LEVELS OF HARDWARE MODELING 2 10 COMPARISON OF MODELS OF COMPUTATION 2 10 1 CRITERIA 2 10 2 UML 2 10 3 PTOLEMY II 2 11 ASSIGNMENTS 3 EMBEDDED SYSTEM HARDWARE INPUT SENSORS DISCRETIZATION OF TIME: SAMPLE-AND-HOLD CIRCUITS DISCRETIZATION OF VALUES: A/D-CONVERTERS PROCESSING UNITS OVERVIEW APPLICATION-SPECI?C CIRCUITS (ASICS) PROCESSORS RECON?GURABLE LOGIC MEMORIES COMMUNICATION ELECTRICAL ROBUSTNESS GUARANTEEING REAL-TIME BEHAVIOR EXAMPLES OUTPUT D/A-CONVERTERS SAMPLING THEOREM ACTUATORS SECURE HARDWARE 4 SYSTEM SOFTWARE EMBEDDED OPERATING SYSTEMS GENERAL REQUIREMENTS REAL-TIME OPERATING SYSTEMS VIRTUAL MACHINES RESOURCE ACCESS PROTOCOLS ERIKA HARDWARE ABSTRACTION LAYERS MIDDLEWARE OSEK/VDX COM CORBA MPI POSIX THREADS (PTHREADS) OPENMP UPNP, DPWS AND JXTA REAL-TIME DATABASES 5 EVALUATION AND VALIDATION MULTI-OBJECTIVE OPTIMIZATION RELEVANT OBJECTIVES PERFORMANCE EVALUATION EARLY PHASES WCET ESTIMATION REAL-TIME CALCULUS ENERGY AND POWER MODELS THERMAL MODELS RISK- AND DEPENDABILITY ANALYSIS SIMULATION RAPID PROTOTYPING AND EMULATION FORMAL VERI?CATION 6 APPLICATION MAPPING PROBLEM DE?NITION SCHEDULING IN REAL-TIME SYSTEMS CLASSI?CATION OF SCHEDULING ALGORITHMS APERIODIC SCHEDULING WITHOUT PRECEDENCE CONSTRAINTS APERIODIC SCHEDULING WITH PRECEDENCE CONSTRAINTS PERIODIC SCHEDULING WITHOUT PRECEDENCE CONSTRAINTS PERIODIC SCHEDULING WITH PRECEDENCE CONSTRAINTS SPORADIC EVENTS HARDWARE/SOFTWARE PARTITIONING COOL MAPPING TO HETEROGENEOUS MULTI-PROCESSORS 7 OPTIMIZATION TASK LEVEL CONCURRENCY MANAGEMENT HIGH-LEVEL OPTIMIZATIONS FLOATING-POINT TO ?XED-POINT CONVERSION SIMPLE LOOP TRANSFORMATIONS LOOP TILING/BLOCKING LOOP SPLITTING ARRAY FOLDING COMPILERS FOR EMBEDDED SYSTEMS ENERGY-AWARE COMPILATION MEMORY-ARCHITECTURE AWARE COMPILATION RECONCILING COMPILERS AND TIMING ANALYSIS COMPILATION FOR DIGITAL SIGNAL PROCESSORS COMPILATION FOR MULTIMEDIA PROCESSORS COMPILATION FOR VLIW PROCESSORS COMPILATION FOR NETWORK PROCESSORS COMPILER GENERATION, RETARGETABLE COMPILERS AND DE- SIGN SPACE EXPLORATION POWER MANAGEMENT AND THERMAL MANAGEMENT DYNAMIC VOLTAGE SCALING (DVS) DYNAMIC POWER MANAGEMENT (DPM) 8 TEST TEST PROCEDURES TEST PATTERN GENERATION FOR GATE LEVEL MODELS SELF-TEST PROGRAMS EVALUATION OF TEST PATTERN SETS AND SYSTEM ROBUSTNESS FAULT COVERAGE FAULT SIMULATION FAULT INJECTION DESIGN FOR TESTABILITY MOTIVATION SCAN DESIGN SIGNATURE ANALYSIS PSEUDO-RANDOM TEST PATTERN GENERATION THE BUILT-IN LOGIC BLOCK OBSERVER (BILBO)