VLSI ELECTRONICS MICROSTRUCTURE SCIENCE
CONTENTS CHAPTER CONSIDERATIONS FOR SELECTION AND APPLICATION OF FOREIGN ELECTRONIC COMPONENT BASES IN DESIGNING DOMESTIC SPACECRAFT 1 1 GENERAL PROBLEMS OF ECB SELECTION FOR REE OF SPACE APPLICATION 1 2 RESTRICTION ON EXPORT OF FOREIGN-MADE ELECTRONIC COMPONENTS TO RUSSIA 1 2 1 RESTRICTION OF ECB EXPORTS FROM THE UNITED STATES 1 2 2 RESTRICTION ON ECB EXPORTS FROM EUROPE AND OTHER COUNTRIES 1 2 3 INTERNATIONAL EXPORT CONTROL ORGANIZATIONS 1 3 PECULIARITIES OF APPLICATION OF FOREIGN-MADE INDUSTRIAL ECB IN ROCKET AND SPACE TECHNOLOGY 1 4 COUNTERFEIT MICROELECTRONIC PRODUCTS AND METHODS OF THEIR DETECTION 1 4 1 TYPES OF COUNTERFEIT COMPONENTS 1 4 2 EFFECTIVE METHODS OF DETECTING COUNTERFEIT PRODUCTS 1 4 3 ELECTRIC TESTING OF MICROELECTRONIC PRODUCTS FOR SPACE APPLICATION 1 5 PECULIARITIES OF SELECTION AND APPLICATION OF FOREIGN PROCESSORS IN DOMESTIC SPACECRAFT 1 5 1 APPLICATION ASPECTS OF FOREIGN PROCESSORS IN DOMESTIC SPACECRAFT 1 5 2 VERSIONS AND QUALIFICATIONS OF UT 699 AND GR 712 MICROPROCESSORS 1 5 3 ARCHITECTURE AND HARDWARE FEATURES OF UT 699 AND GR MICROPROCESSORS OF LEON 3FT FAMILY 1 5 4 PECULIARITIES OF MICROPROCESSOR LEON 3 PROGRAMMING 1 6 RADIATION-TOLERANT DC CONVERTERS FOR SPACE AND MILITARY APPLICATIONS 1 6 1 TOTAL IONIZING DOSE (TID) 1 6 2 ENHANCED LOW-DOSE RATE SENSITIVITY (ELDRS) 1 6 3 SINGLE EVENT EFFECTS (SEE) 1 6 4 ANALYSIS OF PARAMETER LIMITS IN WORST-CASE SCENARIOS 1 6 5 MIL-PRF-38534 STANDARD CLASS K REQUIREMENTS 1 6 6 ABSENCE OF OPTOCOUPLERS IN HYBRID DC-DC CONVERTERS 1 7 BEST PRACTICES OF WORK ARRANGEMENT FOR PRODUCING ELECTRONIC COMPONENTS OF SPACE SYSTEM ON-BOARD EQUIPMENT 1 8 ACCELERATED RELIABILITY TESTING OF ECB SA 1 9 ANALYSIS OF TEST RESULTS FOR MICROCIRCUITS PURCHASED IN RUSSIA BETWEEN 2009 AND REFERENCES CHAPTER PECULIARITIES OF THE TECHNOLOGICAL PROCESS OF PRODUCTION AND BASIC CONSTRUCTIONS OF SUBMICRON TRANSISTORS AND SCHOTTKY DIODES? 2 1 ON THE TERMINOLOGY OF SUBMICRON MICROELECTRONICS 2 2 TENDENCIES AND PERSPECTIVES OF MODERN TECHNOLOGY DEVELOPMENT IN MICROELECTRONICS 2 2 1 SCALING PROBLEM 2 2 2 MODERN SUBMICRON TECHNOLOGY: AN EXAMPLE OF ITS IMPLEMENTATION FOR MICROPROCESSOR PRODUCTION 2 3 PECULIARITIES OF SUBMICRON MOS TRANSISTORS 2 3 1 MOS TRANSISTORS STRUCTURES IN VLSIC 2 3 2 METHODS TO IMPROVE MOS TRANSISTOR PROPERTIES 2 3 3 MOS TRANSISTORS WITH THE STRUCTURE SILICON ON INSULATOR 2 3 4 TRANSISTORS WITH DOUBLE, TRIPLE, AND CYLINDRICAL GATES 2 3 5 OTHER TYPES OF TRANSISTOR STRUCTURES 2 3 6 THE PECULIARITIES OF TRANSISTORS FOR ANALOG APPLICATIONS 2 4 CONSTRUCTIONAL-TECHNOLOGICAL PECULIARITIES OF HIGH-TEMPERATURE SCHOTTKY DIODES 2 4 1 PHYSICAL BASICS OF SCHOTTKY DIODE FUNCTIONING 2 4 2 DESIGN-TECHNOLOGICAL PECULIARITIES OF THE FORMATION OF HIGH- TEMPERATURE SCHOTTKY DIODES 2 4 3 METHODS OF ENSURING MINIMUM REVERSE CURRENT AND MINIMUM DIRECT VOLTAGE 2 4 4 METHODS OF ENSURING MINIMUM DIRECT VOLTAGE AND MAXIMUM REVERSE VOLTAGE 2 5 DESIGN-TECHNOLOGICAL PECULIARITIES OF FORMING THE STRUCTURES OF THE SCHOTTKY DIODE WITH INCREASED RESISTANCE TO STATIC ELECTRICITY DISCHARGES SELECTED BIBLIOGRAPHY ENERGY CONSUMPTION MINIMIZATION METHODS FOR MICROELECTRONIC DEVICES 3 1 MAIN TRENDS IN ENERGY CONSUMPTION PARAMETERS OF MICROELECTRONIC DEVICES 3 2 WAYS TO REDUCE THE POWER DISSIPATION RATE IN CMOS LSIC 3 3 MAIN SOURCES OF POWER DISSIPATION IN CMOS LSICS 3 4 LOGICAL DESIGN OF CMOS LSIC WITH REDUCED POWER CONSUMPTION 3 4 1 BASIC LOGICAL SYNTHESIS OF CMOS MICROCIRCUITS WITH REDUCED POWER CONSUMPTION 3 4 2 DETERMINING THE SOURCES OF POWER DISSIPATION IN CMOS MICROCIRCUITS 3 4 3 PROBABILISTIC ASSESSMENT OF OPTIMIZATION OPTIONS BASED ON PREDICTED SWITCHING ACTIVITY OF MICROCIRCUIT UNITS 3 4 4 THE CHOICE OF ELEMENT BASIS WHILE DESIGNING CMOS VLSICS WITH REDUCED POWER CONSUMPTION 3 4 5 LOGIC SYNTHESIS OF CMOS LSIC IN ELEMENT LIBRARY BASIS 3 4 6 OPTIMIZATION OF TWO-LEVEL LOGICAL CIRCUITS REGARDING POWER DISSIPATION 3 4 7 SELECTION OF BASIC GATES OF TECHNOLOGY-INDEPENDENT FUNCTIONAL CIRCUITS 3 4 8 OPTIMIZATION OF MULTILEVEL LOGICAL CIRCUITS COMPOSED OF MULTI-INPUT GATES 3 4 9 OPTIMIZATION OF MULTILEVEL LOGICAL CIRCUITS COMPOSED OF TWO-INPUT GATES 3 4 10 TECHNOLOGICAL REPRESENTATION 3 4 11 ESTIMATION OF POWER CONSUMPTION BY THE DESIGNED CMOS LSICS AT THE LOGICAL AND CIRCUIT LEVELS 3 4 12 TECHNOLOGY OF DESIGNING CMOS LSICS WITH REDUCED POWER CONSUMPTION USING PSLS 3 4 13 PSLS SOFTWARE COMPLEX ARCHITECTURE 3 4 14 FUNCTIONAL CAPABILITIES OF THE SOFTWARE COMPLEX PSLS 3 5 ORGANIZATION PECULIARITIES OF THE REDUCED POWER CONSUMPTION IN MODERN INTERFACE LSICS 3 5 1 RS-485 INTERFACE TRANSMITTER-RECEIVER MICROCIRCUITS 3 5 2 RS-232 INTERFACE TRANSCEIVER MICROCIRCUITS 3 5 3 DESIGN AND SCHEMATIC-TECHNICAL PECULIARITIES OF DESIGNING INTERFACE OF IC VOLTAGE COMPARATORS WITH REDUCED SUPPLY VOLTAGE 3 5 4 PECULIARITIES OF DESIGNING ELECTRICAL CIRCUITS OF TRANSMITTER UNITS OF INTERFACE LSICS WITH REDUCED POWER CONSUMPTION 3 5 5 THERMALLY INDEPENDENT BASE VOLTAGE SOURCE, EQUAL TO THE WIDTH OF THE BANDGAP OF THE SEMICONDUCTOR 3 5 6 DESIGN OPTIONS FOR THERMALLY INDEPENDENT BASE VOLTAGE SOURCES 3 5 7 CIRCUIT CONFIGURATION METHODS OF INCREASING THE RESISTANCE OF MICROCIRCUITS TO THE HOT ELECTRONS EFFECT PECULIARITIES OF RADIATION IMPACT ON SUBMICRON INTEGRATED CIRCUITS 4 1 PHYSICAL MECHANISMS OF RADIATION IMPACT ON SUBMICRON CMOS INTEGRATED CIRCUITS 4 1 1 PROPERTY RECOVERY FOR RADIATION-EXPOSED MIC DEVICES 4 1 2 IMPACT OF THE EXPOSURE CONDITIONS ON THE RADIATION TOLERANCE OF MIC DEVICES 4 2 INFLUENCE OF RADIATION ON ANALOG BIPOLAR INTEGRATED CIRCUITS 4 2 1 RADIATION EFFECTS IN INTEGRATED OPERATIONAL AMPLIFIERS 4 2 2 RADIATION EFFECTS IN INTEGRATED VOLTAGE COMPARATORS 4 3 THE MAIN METHODS OF ENSURING RADIATION TOLERANCE OF INTEGRATED CIRCUITS 4 4 RADIATION TOLERANCE OF MODERN AND ADVANCED ICS 4 5 RECOMMENDED SET OF TEST ELEMENTS FOR EXPERIMENTAL RESEARCH ON THE RADIATION IMPACT ON THE SILICON MICROCIRCUIT PROPERTIES 4 5 1 ELEMENT BASE OF LOGIC CMOS OF INTEGRATED CIRCUITS 4 5 2 THE ELEMENT BASE OF ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES (EEPROM) 4 5 3 LOGIC CMOS IC 4 5 4 MEMORY CMOS LSIC 4 5 5 CMOS LSIC SRAM ON THE BASIS OF SOI STRUCTURES 4 5 6 BICMOS LSIC 4 6 EQUIPMENT AND METHODS OF IRRADIATING TEST STRUCTURES AND STUDIED SAMPLES OF MICROCIRCUITS 4 7 METHODS OF MEASURING ELECTRIC PARAMETERS OF TEST STRUCTURES AFTER IRRADIATION 4 7 1 METHODS OF EEPROM PARAMETERS’ CONTROL 4 8 THE EXPERIMENTAL RESEARCH RESULTS OF THE PENETRATING RADIATION IMPACT ON THE PARAMETERS OF BIPOLAR TRANSISTOR STRUCTURES 4 9 EXPERIMENTAL RESEARCH OF THE IONIZING RADIATION IMPACT ON THE PARAMETERS OF BIPOLAR ANALOG INTEGRATED CIRCUITS 4 10 RESULTS OF EXPERIMENTAL RESEARCH ON THE IMPACT OF IONIZING RADIATION ON THE PARAMETERS OF TRANSISTOR MOS STRUCTURES AND INTEGRATED CIRCUITS BASED ON THEM 4 10 1 THE STUDY OF THE GAMMA-RADIATION IMPACT ON THE PARAMETERS OF TRANSISTOR MOS STRUCTURES 4 10 2 EXPERIMENTAL STUDIES OF THE GAMMA-RADIATION IMPACT ON THE MOS CAPACITORS AND TRANSISTOR MOS STRUCTURE PARAMETERS: SUBMICRON CMOS IC ELEMENTS 4 10 3 PECULIARITIES OF THE GAMMA-RADIATION IMPACT ON THE PARAMETERS OF THE MOS CELL OF EEPROM 4 10 4 EXPERIMENTAL RESEARCH OF THE PENETRATING RADIATION IMPACT ON THE PARAMETERS OF LOGIC CMOS IC 4 10 5 IMPACT OF THE IONIZING RADIATION ON THE PARAMETERS OF MEMORY CMOS LSIC 4 10 6 EXPERIMENTAL STUDY OF THE RADIATION IMPACT ON THE PARAMETERS OF MOS/SOI STRUCTURES AND CMOS LSI RAM BASED ON THEM 4 10 7 EXPERIMENTAL RESEARCH ON IMPACT OF THE PENETRATING RADIATION ON THE PARAMETERS OF LOGIC BICMOS LSIC 4 11 PECULIARITIES OF USING SIMULATION METHODS IN STUDYING OF THE RADIATION EFFECTS IN BICMOS MICROCIRCUITS 4 12 PECULIARITIES OF THE MECHANISMS OF THE INFLUENCE OF SPACE FACTORS ON THE FORMATION OF LOCAL RADIATION EFFECTS 4 13 EXPERIMENTAL STUDIES OF RADIATION-RESISTANT HYBRID DC/DC CONVERTERS OF CHINESE MANUFACTURE METHODS OF PREDICTION AND INCREASE OF THE RADIATION TOLERANCE OF BIPOLAR AND CMOS INTEGRATED MICROCIRCUITS 5 1 PREDICTION METHODS OF RADIATION TOLERANCE OF CMOS LSI 5 1 1 CALCULATION-EXPERIMENTAL PREDICTION METHODS OF MOS TOOL RADIATION TOLERANCE 5 1 2 PREDICTION (SELECTION) METHOD OF CMOS IC ACCORDING TO RADIATION TOLERANCE 5 2 CALCULATION-EXPERIMENTAL METHODS FOR CALCULATION OF RADIATION TOLERANCE OF BIPOLAR AND BICMOS TOOLS 5 3 CALCULATION-EXPERIMENTAL METHOD OF PREDICTING RADIATION TOLERANCE OF EEPROM MOS MEMORY ELEMENTS 5 4 METHODS OF INCREASING IC RESISTANCE TO THE IMPACT OF PENETRATING RADIATION 5 4 1 CONSTRUCTION-TECHNOLOGICAL METHODS OF INCREASING RADIATION TOLERANCE OF CMOS AND BICMOS MICROCIRCUITS 5 4 2 STANDARD CONSTRUCTION AND CIRCUIT CONFIGURATION METHODS OF INCREASING RADIATION TOLERANCE OF ICS 5 4 3 NEW CONSTRUCTION AND CIRCUIT CONFIGURATION METHODS OF INCREASING RADIATION TOLERANCE OF CMOS LSIC ANALYSIS OF PROBLEMS OF DESIGNING VERY-HIGH-SPEED MICROELECTRONIC DEVICES AND SYSTEMS BASED ON THEM 6 1 PROBLEMS OF SCALING SUBMICRON MICROCIRCUITS 6 2 TENDENCIES AND PROBLEMS OF DESIGNING SILICON INTEGRATED MICROCIRCUITS WITH THE DEEP SUBMICRON DESIGN RULES 6 2 1 TENDENCIES OF SCALING AND PROBLEMS OF DESIGNING SILICON SUBMICRON ICS 6 2 2 PROBLEM OF POWER CONSUMPTION IN SUBMICRON IC 6 2 3 MONITORING DISSIPATED POWER DISTRIBUTION ACROSS THE CHIP AREA AT THE DESIGN STAGE 6 3 LEAKAGE CURRENTS AND STATIC POWER CONSUMPTION IN THE STRUCTURE OF A SILICON MOS TRANSISTOR 6 3 1 POWER CONSUMPTION IN SUBMICRON CMOS CIRCUITS 6 3 2 ANALYSIS OF THE CURRENTS FLOWING IN A SUBMICRON SILICON MOS TRANSISTOR 6 3 3 PHYSICAL CAUSES OF LEAKAGE CURRENTS IN SUBMICRON SILICON TRANSISTORS 6 3 4 ANALYSIS OF THE POWER STATIC CONSUMPTION VALUE OF A MOS TRANSISTOR 6 3 5 PECULIARITIES OF DESIGNING SUBMICRON ANALOG ICS TAKING INTO ACCOUNT STATIC POWER CONSUMPTION 6 3 6 PECULIARITIES OF DESIGNING SUBMICRON ANALOG-DIGITAL ICS TAKING INTO ACCOUNT STATIC POWER CONSUMPTION 6 4 DYNAMIC POWER CONSUMPTION IN A TYPICAL STRUCTURE OF A SUBMICRON MOS TRANSISTOR 6 4 1 SUBMICRON DIGITAL ICS WITH REFERENCE DELAY VALUE 6 4 2 SIGNAL DISTRIBUTION DELAY AT INTERCONNECTIONS 6 4 3 METHODS OF REDUCING SWITCHING POWER CONSUMPTION 6 4 4 ANALYSIS AND CALCULATION OF DYNAMIC POWER CAUSED BY LEAKAGE CURRENTS 6 4 5 ANALYSIS OF DYNAMIC POWER CONSUMPTION OF SILICON MICROCIRCUITS 6 5 INFLUENCE OF TEMPERATURE AND PROCESS PARAMETERS SPREAD ON CHARACTERISTICS OF SILICON SUBMICRON ICS 6 5 1 DEPENDENCE OF LEAKAGE CURRENTS ON TEMPERATURE 6 5 2 PROCESS PARAMETER SPREAD AND LEAKAGE CURRENTS 6 6 PECULIARITIES OF DESIGNING LAYOUT OF ANALOG ICS WITH DEEP SUBMICRON DESIGN RULES 6 6 1 INFLUENCE OF SUPPLY VOLTAGE REDUCTION 6 6 2 SCALING AND DELAY OF SIGNAL DISTRIBUTION AT INTERCONNECTIONS 6 7 GENERAL CONCLUSIONS AND RECOMMENDATIONS DESIGNING SPACE APPLICATION MICROCIRCUITS BASED ON SOS AND SOI STRUCTURES 7 1 RADIATION-TOLERANT CMOS LSI CIRCUIT BASED ON SOI STRUCTURES 7 2 IMPACT OF IONIZING RADIATION EXPOSURE ON SILICON AND SILICON DIOXIDE 7 2 1 RADIATION EFFECTS IN SILICON UNDER IRRADIATION 7 2 2 PROPERTIES OF THE SI/SIO2 INTERFACE REGION 7 2 3 IMPACT OF IONIZING RADIATION EXPOSURE ON DIELECTRIC LAYERS 7 2 4 RADIATION PROCESSES WITHIN THE BURIED DIELECTRIC OF SILICON-ON- INSULATOR STRUCTURES 7 2 5 COMPARISON OF RADIATION PROPERTIES OF SOI STRUCTURES OBTAINED BY VARIOUS METHODS 7 3 PHYSICAL PHENOMENA IN MOS/SOI TRANSISTORS UNDER CONDITIONS OF IR EXPOSURE 7 3 1 IONIZING RADIATION 7 3 2 FULL-DOSE EFFECTS 7 3 3 IMPULSE IRRADIATION EFFECTS 7 4 RESULTS OF EXPERIMENTAL RESEARCH OF SAMPLES OF THE CMOS LSIC ELEMENT BASE ON SOI STRUCTURES 7 4 1 COMPOSITION OF TEST ELEMENTS 7 4 2 EXPERIMENT PROCEDURE 7 4 3 EXPERIMENTAL RESULTS SYSTEM-ON-CHIP AND SYSTEM-IN-PACKAGE 8 1 GENERAL TRENDS IN THE DEVELOPMENT OF CHIP PACKAGING TECHNOLOGY 8 2 BGA TECHNOLOGY OF CHIP ASSEMBLY 8 3 TECHNOLOGY FOR CHIP MOUNTING ON THE BOARD 8 4 MULTICHIP MODULES AND PRINTED BOARDS 8 5 MAIN TRENDS IN DEVELOPMENT OF PACKAGING TECHNOLOGIES FOR MICROELECTRONIC DEVICES OF SPACE-RELATED APPLICATION 8 5 1 TREND TOWARDS DECREASE IN THE PACKAGE LEAD PITCH 8 5 2 WAFER LEADS PACKAGING (WLP) 8 6 PECULIARITIES OF THE PACKAGING TECHNOLOGIES FOR SHF CIRCUIT ON THE BOARD 8 7 TECHNOLOGIES OF TSV CHIP ASSEMBLY FOR SPACE-RELATED APPLICATIONS 8 8 FEATURES OF THE ASSEMBLY OF 3D PRODUCTS WITH FLIP-CHIP TECHNOLOGY USED 8 9 FEATURES OF THE APPLICATION OF ADHESIVES AND PASTES DURING 3D ASSEMBLY 8 10 SYSTEM-IN-PACKAGE ELECTRONIC UNITS FOR MILITARY SPACE MICROELECTRONICS 8 11 FEATURES OF AUTOMATIC DESIGN TOOLS: SYSTEMS-IN-PACKAGE 8 11 1 RF MODULE DESIGN 8 12 CONSIDERING FEATURES OF DEEP SUBMICRON TECHNOLOGY WHEN DESIGNING VLSICS FOR SIPS 8 13 THE IMPACT OF SIP ON THE EVOLUTION OF THE CONCEPTS OF SATELLITE SYSTEM CONSTRUCTION 8 14 FEATURES OF SELECTION AND APPLICATION OF KNOWN GOOD DIE FOR SIP 8 15 PACKAGE DESIGNS WITH INTEGRATED RADIATION PROTECTION SCREENS 8 16 SHF APPLICATIONS OF MEMS TECHNOLOGIES 8 16 1 FEATURES OF IMPLEMENTATION OF RADIO FREQUENCY MEMS/CMOS DEVICES 8 16 2 RADIO-FREQUENCY MEMS SWITCHES 8 16 3 RADIO-FREQUENCY MEMS CONDENSERS OF VARIABLE CAPACITY 8 16 4 INTEGRATED MEMS/CMOS RESONATORS 8 16 5 MEMS TECHNOLOGIES IN THE TASK OF SYSTEM INTEGRATION OF RADAR INSTALLATIONS 8 17 GOLD AND ALUMINUM APPLICATION FEATURES IN POWER MICROWAVE TRANSISTOR ASSEMBLY TECHNIQUE METHODS FOR REJECTION OF SILICON MICROCIRCUITS WITH HIDDEN DEFECTS DURING MASS PRODUCTION 9 1 FORMULATION OF THE PROBLEM FOR THE CASE OF PARAMETRIC CONTROL OF INTEGRATED CIRCUITS AT NOMINAL OPERATING MODES 9 2 METHODS FOR DETERMINATION OF SENSITIVITY COEFFICIENTS FOR OUTPUT PARAMETERS OF BIPOLAR INTEGRATED MICROCIRCUITS 9 3 DETECTION OF MICROCIRCUITS WITH HIDDEN DEFECTS BASED ON THE ANALYSIS OF OPERATING RANGE BOUNDARIES 9 4 EVALUATION OF NUMERICAL VALUES OF RELIABILITY INDEXES BASED ON THE RESULTS OF EXPERIMENTAL TESTS OF INTEGRATED MICROCIRCUITS 9 5 STUDYING THE MECHANISMS OF INFLUENCE OF HIDDEN DEFECTS ON NUMERICAL VALUES OF THE BIPOLAR IC’S BASIC STATISTIC PARAMETERS 9 6 ANALYSIS OF A MODEL OF MATHEMATICAL PROCESSING OF FORCED TEST RESULTS OF CMOS MICROCIRCUITS 9 7 MAIN METHODS OF DETECTION AND REJECTION OF POTENTIALLY UNRELIABLE CIRCUITS IN CONDITIONS OF MASS PRODUCTION 9 7 1 METHOD FOR DETERMINING POTENTIALLY UNSTABLE DEVICES USING ELECTROSTATIC DISCHARGE 9 7 2 AN UPGRADED METHOD FOR IMPLEMENTATION OF MICROELECTRONIC DEVICES BURN-IN PROCEDURE 9 7 3 METHOD FOR DETECTION OF INTEGRATED CIRCUITS WITH INCREASED RELIABILITY BASED ON THE CRITICAL SUPPLY VOLTAGE PARAMETER 9 7 4 METHOD FOR REJECTION OF POTENTIALLY UNRELIABLE MICROCIRCUITS BY DYNAMIC CURRENT CONSUMPTION 9 7 5 METHOD OF SUPPLY VOLTAGE REDUCTION