VLIW MICROPROCESSOR HARDWARE DESIGN FOR ASICS AND FPGA

By PAUL TAYLOR

CONTENTS CHAPTER 1 INTRODUCTION TYPES OF MICROPROCESSORS TYPES OF MICROPROCESSOR ARCHITECTURE CHAPTER 2 DESIGN METHODOLOGY TECHNICAL SPECI?CATION INSTRUCTION SET OF VLIW MICROPROCESSOR DE?NITION OF OPCODE FOR VLIW INSTRUCTION SET DE?NITION OF VLIW INSTRUCTION ARCHITECTURAL SPECI?CATION MICROARCHITECTURE SPECI?CATION CHAPTER 3 RTL CODING,TESTBENCHING, AND SIMULATION CODING RULES RTL CODING MODULE FETCH RTL CODE MODULE DECODE RTL CODE MODULE REGISTER ?LE RTL CODE MODULE EXECUTE RTL CODE MODULE WRITEBACK RTL CODE MODULE VLIWTOP RTL CODE TESTBENCHES AND SIMULATION CREATING AND USING A TESTPLAN CODE COVERAGE SYNTHESIS STANDARD CELL LIBRARY DESIGN CONSTRAINTS SYNTHESIS TWEAKS FORMAL VERI?CATION PRE-LAYOUT STATIC TIMING ANALYSIS LAYOUT MANUAL/CUSTOM LAYOUT SEMI-CUSTOM/AUTO LAYOUT AUTO PLACE AND ROUTE DRC / LVS RC EXTRACTION POST-LAYOUT LOGIC VERI?CATION POST-LAYOUT PERFORMANCE VERI?CATION TAPEOUT LINKING FRONT END AND BACK END POWER CONSUMPTION ASIC DESIGN TESTABILITY CHAPTER 4 FPGA IMPLEMENTATION FPGA VERSUS ASIC FPGA DESIGN METHODOLOGY TESTING FPGA STRUCTURED ASIC