VLSI ELECTRONICS MICROSTRUCTURE SCIENCE
CHAPTER INTEGRATED-CIRCUIT DEVICES AND MODELLING SEMICONDUCTORS AND PN JUNCTIONS DIODES REVERSE-BIASED DIODES GRADED JUNCTIONS LARGE-SIGNAL JUNCTION CAPACITANCE FORWARD-BIASED JUNCTIONS JUNCTION CAPACITANCE OF FORWARD-BIASED DIODE SMALL-SIGNAL MODEL OF A FORWARD-BIASED DIODE SCHOTTKY DIODES MOS TRANSISTORS SYMBOLS FOR MOS TRANSISTORS BASIC OPERATION LARGE-SIGNAL MODELLING BODY EFFECT P-CHANNEL TRANSISTORS LOW-FREQUENCY SMALL-SIGNAL MODELLING IN THE ACTIVE REGION HIGH-FREQUENCY SMALL-SIGNAL MODELLING IN THE ACTIVE REGION SMALL-SIGNAL MODELLING IN THE TRIODE AND CUTOFF REGIONS ANALOG FIGURES OF MERIT AND TRADE-OFFS DEVICE MODEL SUMMARY CONSTANTS DIODE EQUATIONS MOS TRANSISTOR EQUATIONS ADVANCED MOS MODELLING SUBTHRESHOLD OPERATION MOBILITY DEGRADATION SUMMARY OF SUBTHRESHOLD AND MOBILITY DEGRADATION EQUATIONS PARASITIC RESISTANCES SHORT-CHANNEL EFFECTS LEAKAGE CURRENTS SPICE MODELLING PARAMETERS DIODE MODEL ADVANCED SPICE MODELS OF MOS TRANSISTORS PASSIVE DEVICES RESISTORS CAPACITORS APPENDIX DIODE EXPONENTIAL RELATIONSHIP DIODE-DIFFUSION CAPACITANCE MOS THRESHOLD VOLTAGE AND THE BODY EFFECT MOS TRIODE RELATIONSHIP KEY POINTS REFERENCES PROBLEMS PROCESSING AND LAYOUT CMOS PROCESSING THE SILICON WAFER PHOTOLITHOGRAPHY AND WELL DEFINITION DIFFUSION AND ION IMPLANTATION CHEMICAL VAPOR DEPOSITION AND DEFINING THE ACTIVE REGIONS TRANSISTOR ISOLATION GATE-OXIDE AND THRESHOLD-VOLTAGE ADJUSTMENTS POLYSILICON GATE FORMATION IMPLANTING THE JUNCTIONS, DEPOSITING SIO2, AND OPENING CONTACT HOLES ANNEALING, DEPOSITING AND PATTERNING METAL, AND OVERGLASS DEPOSITION ADDITIONAL PROCESSING STEPS CMOS LAYOUT AND DESIGN RULES SPACING RULES PLANARITY AND FILL REQUIREMENTS ANTENNA RULES LATCH-UP VARIABILITY AND MISMATCH SYSTEMATIC VARIATIONS INCLUDING PROXIMITY EFFECTS PROCESS VARIATIONS RANDOM VARIATIONS AND MISMATCH ANALOG LAYOUT CONSIDERATIONS TRANSISTOR LAYOUTS CAPACITOR MATCHING RESISTOR LAYOUT NOISE CONSIDERATIONS BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS SIMPLE CMOS CURRENT MIRROR COMMON-SOURCE AMPLIFIER SOURCE-FOLLOWER OR COMMON-DRAIN AMPLIFIER COMMON-GATE AMPLIFIER SOURCE-DEGENERATED CURRENT MIRRORS CASCODE CURRENT MIRRORS CASCODE GAIN STAGE MOS DIFFERENTIAL PAIR AND GAIN STAGE FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS FREQUENCY RESPONSE OF LINEAR SYSTEMS MAGNITUDE AND PHASE RESPONSE FIRST-ORDER CIRCUITS SECOND-ORDER LOW-PASS TRANSFER FUNCTIONS WITH REAL POLES BODE PLOTS SECOND-ORDER LOW-PASS TRANSFER FUNCTIONS WITH COMPLEX POLES FREQUENCY RESPONSE OF ELEMENTARY TRANSISTOR CIRCUITS HIGH-FREQUENCY MOS SMALL-SIGNAL MODEL MILLER THEOREM AND MILLER EFFECT ZERO-VALUE TIME-CONSTANT ANALYSIS COMMON-SOURCE DESIGN EXAMPLES SOURCE-FOLLOWER AMPLIFIER DIFFERENTIAL PAIR HIGH-FREQUENCY T-MODEL SYMMETRIC DIFFERENTIAL AMPLIFIER SINGLE-ENDED DIFFERENTIAL AMPLIFIER DIFFERENTIAL PAIR WITH ACTIVE LOAD FEEDBACK AMPLIFIERS IDEAL MODEL OF NEGATIVE FEEDBACK BASIC DEFINITIONS GAIN SENSITIVITY BANDWIDTH LINEARITY SUMMARY DYNAMIC RESPONSE OF FEEDBACK AMPLIFIERS STABILITY CRITERIA PHASE MARGIN FIRST- AND SECOND-ORDER FEEDBACK SYSTEMS FIRST-ORDER FEEDBACK SYSTEMS SECOND-ORDER FEEDBACK SYSTEMS HIGHER-ORDER FEEDBACK SYSTEMS COMMON FEEDBACK AMPLIFIERS OBTAINING THE LOOP GAIN, L(S) NON-INVERTING AMPLIFIER TRANSIMPEDANCE (INVERTING) AMPLIFIERS SUMMARY OF KEY POINTS BASIC OPAMP DESIGN AND COMPENSATION TWO-STAGE CMOS OPAMP OPAMP GAIN FREQUENCY RESPONSE SLEW RATE N-CHANNEL OR P-CHANNEL INPUT STAGE SYSTEMATIC OFFSET VOLTAGE OPAMP COMPENSATION DOMINANT-POLE COMPENSATION AND LEAD COMPENSATION COMPENSATING THE TWO-STAGE OPAMP MAKING COMPENSATION INDEPENDENT OF PROCESS AND TEMPERATURE ADVANCED CURRENT MIRRORS WIDE-SWING CURRENT MIRRORS ENHANCED OUTPUT-IMPEDANCE CURRENT MIRRORS AND GAIN BOOSTING WIDE-SWING CURRENT MIRROR WITH ENHANCED OUTPUT IMPEDANCE CURRENT-MIRROR SYMBOL FOLDED-CASCODE OPAMP SMALL-SIGNAL ANALYSIS CURRENT MIRROR OPAMP LINEAR SETTLING TIME REVISITED FULLY DIFFERENTIAL OPAMPS FULLY DIFFERENTIAL FOLDED-CASCODE OPAMP ALTERNATIVE FULLY DIFFERENTIAL OPAMPS LOW SUPPLY VOLTAGE OPAMPS COMMON-MODE FEEDBACK CIRCUITS BIASING, REFERENCES, AND REGULATORS ANALOG INTEGRATED CIRCUIT BIASING BIAS CIRCUITS REFERENCE CIRCUITS REGULATOR CIRCUITS ESTABLISHING CONSTANT TRANSCONDUCTANCE BASIC CONSTANT-TRANSCONDUCTANCE CIRCUIT IMPROVED CONSTANT-TRANSCONDUCTANCE CIRCUITS ESTABLISHING CONSTANT VOLTAGES AND CURRENTS BANDGAP VOLTAGE REFERENCE BASICS CIRCUITS FOR BANDGAP REFERENCES LOW-VOLTAGE BANDGAP REFERENCE CURRENT REFERENCE VOLTAGE REGULATION REGULATOR SPECIFICATIONS FEEDBACK ANALYSIS LOW DROPOUT REGULATORS BIPOLAR DEVICES AND CIRCUITS BIPOLAR-JUNCTION TRANSISTORS ANALOG FIGURES OF MERIT BIPOLAR DEVICE MODEL SUMMARY SPICE MODELING BIPOLAR AND BICMOS PROCESSING BIPOLAR PROCESSING MODERN SIGE BICMOS HBT PROCESSING MISMATCH IN BIPOLAR DEVICES BIPOLAR CURRENT MIRRORS AND GAIN STAGES CURRENT MIRRORS EMITTER FOLLOWER BIPOLAR DIFFERENTIAL PAIR BIPOLAR TRANSISTOR EXPONENTIAL RELATIONSHIP BASE CHARGE STORAGE OF AN ACTIVE BJT NOISE AND LINEARITY ANALYSIS AND MODELLING TIME-DOMAIN ANALYSIS ROOT MEAN SQUARE (RMS) VALUE SNR UNITS OF DBM NOISE SUMMATION FREQUENCY-DOMAIN ANALYSIS NOISE SPECTRAL DENSITY WHITE NOISE 1/F, OR FLICKER, NOISE FILTERED NOISE NOISE BANDWIDTH PIECEWISE INTEGRATION OF NOISE 1/F NOISE TANGENT PRINCIPLE NOISE MODELS FOR CIRCUIT ELEMENTS BIPOLAR TRANSISTORS MOSFETS OPAMPS CAPACITORS AND INDUCTORS SAMPLED SIGNAL NOISE INPUT-REFERRED NOISE NOISE ANALYSIS EXAMPLES OPAMP EXAMPLE BIPOLAR COMMON-EMITTER EXAMPLE CMOS DIFFERENTIAL PAIR EXAMPLE FIBER-OPTIC TRANSIMPEDANCE AMPLIFIER EXAMPLE DYNAMIC RANGE PERFORMANCE TOTAL HARMONIC DISTORTION (THD) THIRD-ORDER INTERCEPT POINT (IP3) SPURIOUS-FREE DYNAMIC RANGE (SFDR) SIGNAL-TO-NOISE AND DISTORTION RATIO (SNDR) COMPARATORS COMPARATOR SPECIFICATIONS INPUT OFFSET AND NOISE HYSTERESIS USING AN OPAMP FOR A COMPARATOR INPUT-OFFSET VOLTAGE ERRORS CHARGE-INJECTION ERRORS MAKING CHARGE-INJECTION SIGNAL INDEPENDENT MINIMIZING ERRORS DUE TO CHARGE-INJECTION SPEED OF MULTI-STAGE COMPARATORS LATCHED COMPARATORS LATCH-MODE TIME CONSTANT LATCH OFFSET EXAMPLES OF CMOS AND BICMOS COMPARATORS INPUT-TRANSISTOR CHARGE TRAPPING EXAMPLES OF BIPOLAR COMPARATORS SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS PERFORMANCE OF SAMPLE-AND-HOLD CIRCUITS TESTING SAMPLE AND HOLDS MOS SAMPLE-AND-HOLD BASICS EXAMPLES OF CMOS S/H CIRCUITS BIPOLAR AND BICMOS SAMPLE-AND-HOLDS TRANSLINEAR GAIN CELL TRANSLINEAR MULTIPLIER CONTINUOUS-TIME FILTERS INTRODUCTION TO CONTINUOUS-TIME FILTERS FIRST-ORDER FILTERS SECOND-ORDER FILTERS INTRODUCTION TO GM-C FILTERS INTEGRATORS AND SUMMERS FULLY DIFFERENTIAL INTEGRATORS FIRST-ORDER FILTER BIQUAD FILTER TRANSCONDUCTORS USING FIXED RESISTORS CMOS TRANSCONDUCTORS USING TRIODE TRANSISTORS TRANSCONDUCTORS USING A FIXED-BIAS TRIODE TRANSISTOR TRANSCONDUCTORS USING VARYING BIAS-TRIODE TRANSISTORS TRANSCONDUCTORS USING CONSTANT DRAIN-SOURCE VOLTAGES CMOS TRANSCONDUCTORS USING ACTIVE TRANSISTORS CMOS PAIR CONSTANT SUM OF GATE-SOURCE VOLTAGES SOURCE-CONNECTED DIFFERENTIAL PAIR INVERTER-BASED DIFFERENTIAL-PAIR WITH FLOATING VOLTAGE SOURCES BIAS-OFFSET CROSS-COUPLED DIFFERENTIAL PAIRS BIPOLAR TRANSCONDUCTORS GAIN-CELL TRANSCONDUCTORS TRANSCONDUCTORS USING MULTIPLE DIFFERENTIAL PAIRS BICMOS TRANSCONDUCTORS TUNABLE MOS IN TRIODE FIXED-RESISTOR TRANSCONDUCTOR WITH A TRANSLINEAR MULTIPLIER FIXED ACTIVE MOS TRANSCONDUCTOR WITH A TRANSLINEAR MULTIPLIER ACTIVE RC AND MOSFET-C FILTERS ACTIVE RC FILTERS MOSFET-C TWO-TRANSISTOR INTEGRATORS FOUR-TRANSISTOR INTEGRATORS R-MOSFET-C FILTERS TUNING CIRCUITRY TUNING OVERVIEW CONSTANT TRANSCONDUCTANCE FREQUENCY TUNING Q-FACTOR TUNING TUNING METHODS BASED ON ADAPTIVE FILTERING INTRODUCTION TO COMPLEX FILTERS COMPLEX SIGNAL PROCESSING COMPLEX OPERATIONS COMPLEX FILTERS FREQUENCY-TRANSLATED ANALOG FILTERS DISCRETE-TIME SIGNALS OVERVIEW OF SOME SIGNAL SPECTRA LAPLACE TRANSFORMS OF DISCRETE-TIME SIGNALS SPECTRA OF DISCRETE-TIME SIGNALS Z-TRANSFORM DOWNSAMPLING AND UPSAMPLING DISCRETE-TIME FILTERS FREQUENCY RESPONSE OF DISCRETE-TIME FILTERS STABILITY OF DISCRETE-TIME FILTERS IIR AND FIR FILTERS BILINEAR TRANSFORM SAMPLE-AND-HOLD RESPONSE SWITCHED-CAPACITOR CIRCUITS BASIC BUILDING BLOCKS SWITCHES NONOVERLAPPING CLOCKS BASIC OPERATION AND ANALYSIS RESISTOR EQUIVALENCE OF A SWITCHED CAPACITOR PARASITIC-SENSITIVE INTEGRATOR PARASITIC-INSENSITIVE INTEGRATORS SIGNAL-FLOW-GRAPH ANALYSIS NOISE IN SWITCHED-CAPACITOR CIRCUITS SWITCH SHARING FULLY DIFFERENTIAL FILTERS BIQUAD FILTERS LOW-Q BIQUAD FILTER HIGH-Q BIQUAD FILTER CHARGE INJECTION SWITCHED-CAPACITOR GAIN CIRCUITS PARALLEL RESISTOR-CAPACITOR CIRCUIT RESETTABLE GAIN CIRCUIT CAPACITIVE-RESET GAIN CIRCUIT CORRELATED DOUBLE-SAMPLING TECHNIQUES OTHER SWITCHED-CAPACITOR CIRCUITS AMPLITUDE MODULATOR FULL-WAVE RECTIFIER PEAK DETECTORS VOLTAGE-CONTROLLED OSCILLATOR SINUSOIDAL OSCILLATOR DATA CONVERTER FUNDAMENTALS IDEAL D/A CONVERTER IDEAL A/D CONVERTER QUANTIZATION NOISE DETERMINISTIC APPROACH STOCHASTIC APPROACH SIGNED CODES PERFORMANCE LIMITATIONS RESOLUTION OFFSET AND GAIN ERROR ACCURACY AND LINEARITY NYQUIST-RATE D/A CONVERTERS DECODER-BASED CONVERTERS RESISTOR STRING CONVERTERS FOLDED RESISTOR-STRING CONVERTERS MULTIPLE RESISTOR-STRING CONVERTERS SIGNED OUTPUTS BINARY-SCALED CONVERTERS BINARY-WEIGHTED RESISTOR CONVERTERS REDUCED-RESISTANCE-RATIO LADDERS R-2R-BASED CONVERTERS CHARGE-REDISTRIBUTION SWITCHED-CAPACITOR CONVERTERS CURRENT-MODE CONVERTERS GLITCHES THERMOMETER-CODE CONVERTERS THERMOMETER-CODE CURRENT-MODE D/A CONVERTERS SINGLE-SUPPLY POSITIVE-OUTPUT CONVERTERS DYNAMICALLY MATCHED CURRENT SOURCES HYBRID CONVERTERS RESISTOR-CAPACITOR HYBRID CONVERTERS SEGMENTED CONVERTERS NYQUIST-RATE A/D CONVERTERS INTEGRATING CONVERTERS SUCCESSIVE-APPROXIMATION CONVERTERS DAC-BASED SUCCESSIVE APPROXIMATION CHARGE-REDISTRIBUTION A/D RESISTOR-CAPACITOR HYBRID SPEED ESTIMATE FOR CHARGE-REDISTRIBUTION CONVERTERS ERROR CORRECTION IN SUCCESSIVE-APPROXIMATION CONVERTERS MULTI-BIT SUCCESSIVE-APPROXIMATION ALGORITHMIC (OR CYCLIC) A/D CONVERTER RATIO-INDEPENDENT ALGORITHMIC CONVERTER PIPELINED A/D CONVERTERS ONE-BIT-PER-STAGE PIPELINED CONVERTER 1 5 BIT PER STAGE PIPELINED CONVERTER PIPELINED CONVERTER CIRCUITS GENERALIZED K-BIT-PER-STAGE PIPELINED CONVERTERS FLASH CONVERTERS ISSUES IN DESIGNING FLASH A/D CONVERTERS TWO-STEP A/D CONVERTERS TWO-STEP CONVERTER WITH DIGITAL ERROR CORRECTION INTERPOLATING A/D CONVERTERS FOLDING A/D CONVERTERS TIME-INTERLEAVED A/D CONVERTERS OVERSAMPLING CONVERTERS OVERSAMPLING WITHOUT NOISE SHAPING QUANTIZATION NOISE MODELLING WHITE NOISE ASSUMPTION OVERSAMPLING ADVANTAGE THE ADVANTAGE OF 1-BIT D/A CONVERTERS OVERSAMPLING WITH NOISE SHAPING NOISE-SHAPED DELTA-SIGMA MODULATOR FIRST-ORDER NOISE SHAPING SWITCHED-CAPACITOR REALIZATION OF A FIRST-ORDER A/D CONVERTER SECOND-ORDER NOISE SHAPING NOISE TRANSFER-FUNCTION CURVES QUANTIZATION NOISE POWER OF 1-BIT MODULATORS ERROR-FEEDBACK STRUCTURE SYSTEM ARCHITECTURES SYSTEM ARCHITECTURE OF DELTA-SIGMA A/D CONVERTERS SYSTEM ARCHITECTURE OF DELTA-SIGMA D/A CONVERTERS DIGITAL DECIMATION FILTERS MULTI-STAGE SINGLE STAGE HIGHER-ORDER MODULATORS INTERPOLATIVE ARCHITECTURE MULTI-STAGE NOISE SHAPING (MASH) ARCHITECTURE BANDPASS OVERSAMPLING CONVERTERS PRACTICAL CONSIDERATIONS STABILITY LINEARITY OF TWO-LEVEL CONVERTERS IDLE TONES DITHERING MULTI-BIT OVERSAMPLING CONVERTERS DYNAMIC ELEMENT MATCHING DYNAMICALLY MATCHED CURRENT SOURCE D/S CONVERTERS DIGITAL CALIBRATION A/D CONVERTER A/D WITH BOTH MULTI-BIT AND SINGLE-BIT FEEDBACK THIRD-ORDER A/D DESIGN EXAMPLE PHASE-LOCKED LOOPS BASIC PHASE-LOCKED LOOP ARCHITECTURE VOLTAGE CONTROLLED OSCILLATOR DIVIDER PHASE DETECTOR LOOP FILER THE PLL IN LOCK LINEARIZED SMALL-SIGNAL ANALYSIS SECOND-ORDER PLL MODEL LIMITATIONS OF THE SECOND-ORDER SMALL-SIGNAL MODEL PLL DESIGN EXAMPLE JITTER AND PHASE NOISE PERIOD JITTER P-CYCLE JITTER ADJACENT PERIOD JITTER OTHER SPECTRAL REPRESENTATIONS OF JITTER PROBABILITY DENSITY FUNCTION OF JITTER ELECTRONIC OSCILLATORS RING OSCILLATORS LC OSCILLATORS PHASE NOISE OF OSCILLATORS JITTER AND PHASE NOISE IN PLLS INPUT PHASE NOISE AND DIVIDER PHASE NOISE VCO PHASE NOISE LOOP FILTER NOISE C H A P T E R MIGHT HAVE AN IMPURITY CONCENTRATION OF CARRIERS/M3, WHEREAS THE P+ AND N+ REGIONS WOULD BE DOPED MORE NN ND = NN ND PN NI ND ------ = NA PP NA = NP NP NI × CARRIERS M ? = PP NA 26 HOLES/M × ELECTRONS/M AL ANODE P+ N+ P– CATHODE PN JUNCTION VT NAND NI ? ? ? ? LN = REVERSE-BIASED DIODES A SILICON DIODE HAVING AN ANODE-TO-CATHODE (I E , P SIDE TO N SIDE) VOLTAGE OF 0 4 V OR LESS WILL NOT BE CONDUCT- ING APPRECIABLE CURRENT IN THIS CASE, IT IS SAID TO BE REVERSE-BIASED IF A DIODE IS REVERSE-BIASED, CURRENT FLOW IS PRIMARILY DUE TO THERMALLY GENERATED CARRIERS IN THE DEPLETION REGION, AND IT IS EXTREMELY SMALL ALTHOUGH THIS REVERSE-BIASED CURRENT IS ONLY WEAKLY DEPENDENT ON THE APPLIED VOLTAGE, THE REVERSE-BIASED CURRENT IS DIRECTLY PROPORTIONAL TO THE AREA OF THE DIODE JUNCTION HOWEVER, AN EFFECT THAT SHOULD NOT BE IGNORED, PARTICULARLY AT HIGH FREQUENCIES, IS THE JUNCTION CAPACITANCE OF A DIODE IN REVERSE-BIASED DIODES, THIS JUNCTION CAPACITANCE IS DUE TO VARYING CHARGE STORAGE IN THE DEPLETION REGIONS AND IS MODELLED AS A DEPLETION CAPACITANCE TO DETERMINE THE DEPLETION CAPACITANCE, WE FIRST STATE THE RELATIONSHIP BETWEEN THE DEPLETION WIDTHS AND THE APPLIED REVERSE VOLTAGE, [SZE, 1981] (1 9) (1 10) HERE, IS THE PERMITTIVITY OF FREE SPACE (EQUAL TO ), IS THE REVERSE-BIAS VOLTAGE OF THE DIODE, AND IS THE RELATIVE PERMITTIVITY OF SILICON (EQUAL TO 11 8) THESE EQUATIONS ASSUME AN ABRUPT JUNCTION WHERE THE DOPING CHANGES INSTANTLY FROM THE N TO THE P SIDE MODIFICATIONS TO THESE EQUATIONS FOR GRADED JUNCTIONS ARE TREATED IN THE NEXT SECTION VT KT Q ------ = T – × JK – × C VT 26 MV NA 25 HOLES/M = ND 22 ELECTRONS/M × CARRIERS/M VR + ( ) Q -------------------------------------- NA ND NA ND + ( ) -------------------------------- 1 VR + ( ) Q -------------------------------------- ND NA NA ND + ( ) ------------------------------- 1 VR + ( ) QND -------------------------------------- 1 VR + ( )ND QNA ? ? ? XN XP ---- NA ND ------ ? NA 0 9 V = XN × ---------------------------------------------------------------------- 1 VR + ( ) NAND NA ND + ------------------- 1 VR + ( )ND [ ] 1 VR + ( ) --------------------------- NAND NA N + D ------------------- 1 + ------------------- = = = VR VR + ( ) --------------------------- 1 = Q 2CJ0?0 GRADED JUNCTIONS ALL OF THE ABOVE EQUATIONS ASSUMED AN ABRUPT JUNCTION WHERE THE DOPING CONCENTRATION CHANGES QUICKLY FROM P TO N OVER A SMALL DISTANCE ALTHOUGH THIS IS A GOOD APPROXIMATION FOR MANY INTEGRATED CIRCUITS, IT IS NOT ALWAYS SO FOR EXAMPLE, THE COLLECTOR-TO-BASE JUNCTION OF A BIPOLAR TRANSISTOR IS MOST COMMONLY REAL- IZED AS A GRADED JUNCTION IN THE CASE OF GRADED JUNCTIONS, THE EXPONENT 1/2 IN (1 15) IS INACCURATE, AND AN EXPONENT CLOSER TO UNITY IS MORE ACCURATE, PERHAPS 0 6 TO 0 7 THUS, FOR GRADED JUNCTIONS, (1 15) IS TYPICALLY WRITTEN AS (1 25) WHERE IS A CONSTANT THAT DEPENDS UPON THE DOPING PROFILE FOR EXAMPLE, A LINEARLY GRADED JUNCTION HAS DIFFERENTIATING (1 25) TO FIND THE DEPLETION CAPACITANCE, WE HAVE (1 26) NA × ----------------------------------------------------------------------------------------------- 304 7 ?F/M – × 30 5 FF = = CT-J 30 5 FF VR + ( ) NAND NA ND + MJ – = MJ MJ 1 ? = CJ NAND NA ND + MJ – VR + ( ) MJ --------------------------- = MJ – --------------?0 MJ – ( ) 2QKS?0ND [ ] 81 5 ?F/M 8 1 FF = CT-J 8 1FF VI Q VI ( ) 2CJ0?0 0 2 FF/(µM) ? 0 2 FF/ ?M ( ) × × 0 02 PF = = (A) THE CIRCUIT USED IN EXAMPLE 1 6; (B) ITS RC APPROXIMATE EQUIVALENT R 10 K? = VIN 1 V T 0 2 FF ?M ( ) JUNCTION CAPACITANCE OF FORWARD-BIASED DIODE WHEN A JUNCTION CHANGES FROM REVERSE BIASED (WITH LITTLE CURRENT THROUGH IT) TO FORWARD BIASED (WITH SIGNIFICANT CURRENT FLOW ACROSS IT), THE CHARGE BEING STORED NEAR AND ACROSS THE JUNCTION CHANGES PART OF THE CHANGE IN CHARGE IS DUE TO THE CHANGE IN THE WIDTH OF THE DEPLETION REGION AND THEREFORE THE AMOUNT OF IMMOBILE CHARGE STORED IN IT THIS CHANGE IN CHARGE IS MODELLED BY THE DEPLETION CAPACITANCE, CJ, SIMILAR TO WHEN THE JUNCTION IS REVERSE BIASED AN ADDITIONAL CHANGE IN CHARGE STORAGE IS NECESSARY TO ACCOUNT FOR THE CHANGE OF THE MINORITY CARRIER CONCENTRATION CLOSE TO THE JUNCTION REQUIRED FOR THE DIFFUSION CURRENT TO EXIST FOR EXAMPLE, IF A FORWARD-BIASED DIODE CURRENT IS TO DOUBLE, THEN THE SLOPES OF THE MINORITY CHARGE STORAGE AT THE DIODE JUNCTION EDGES MUST DOUBLE, AND THIS, IN TURN, IMPLIES THAT THE MINORITY CHARGE STORAGE MUST DOUBLE THIS COMPONENT IS MODELLED BY ANOTHER CAPACITANCE, CALLED THE DIFFUSION CAPACITANCE, AND DENOTED CD THE DIFFUSION CAPACITANCE CAN BE SHOWN (SEE APPENDIX) TO BE (1 45) WHERE IS THE TRANSIT TIME OF THE DIODE NORMALLY IS SPECIFIED FOR A GIVEN TECHNOLOGY, SO THAT ONE CAN CALCULATE THE DIFFUSION CAPACITANCE NOTE THAT THE DIFFUSION CAPAC ITANCE OF A FORWARD-BIASED JUNCTION IS PROPORTIONAL TO THE DIODE CURRENT ID ISE VD VT ? = VD IS AD ND ------ + ? ? ? ? ? ? ? IS AD CD ?TID VT ----- = ?T ?T THE SMALL-SIGNAL MODEL FOR A FORWARD-BIASED JUNCTION RD VD ID AL ANODE CATHODE SCHOTTKY DIODE DEPLETION REGION N+ N – P – N – N – N – N+ N – N – CD COMMONLY USED SYMBOLS FOR N-CHANNEL TRANSISTORS (A) (B) (C) (D) (E) P – AN N-CHANNEL MOS TRANSISTOR (A) , RESULTING IN AN ACCUMULATED CHANNEL (NO CURRENT FLOW); (B) , AND THE CHANNEL IS PRESENT (CURRENT FLOW POSSIBLE FROM DRAIN TO SOURCE) VG << VG >> (B) + + + + + + + + + + N+ N+ P– SUBSTRATE DEPLETION REGION VG >> (A) + + + + + + + + + + N+ N+ P– SUBSTRATE DEPLETION REGION VG << TOX ------------ = THE CHANNEL CHARGE DENSITY FOR N+ N+ VS = VG >> VTN VD > QN ( ) COX VGS VTN – ( ) = QN X ( ) COX VGS VCH X ( ) V – TN – ( ) = QN L ( ) COX VGD VTN – ( ) = DEPLETION REGION INCREASING X VDS FOR VDS NOT CLOSE TO ZERO, THE ID VERSUS VDS RELATIONSHIP IS NO LONGER LINEAR VTN VDG VTN – > VDS-SAT VDG VDS VGS – = VDS VDS-SAT > WHEN VDS IS INCREASED SO THAT , THE CHANNEL BECOMES PINCHED OFF AT THE DRAIN END VGD VTN < N+ N+ VS THE ID VERSUS VDS CURVE FOR AN IDEAL MOS TRANSISTOR FOR , ID IS APPROXIMATELY CONSTANT ID ?NCOX W L ----- VGS VTN – ( )VDS ? ID ?NCOX W L ----- VGS VTN – ( )VDS VDS – = ID ?NCOX LARGE-SIGNAL MODELLING THE TRIODE REGION EQUATION FOR A MOS TRANSISTOR RELATES THE DRAIN CURRENT TO THE GATE-SOURCE AND DRAIN-SOURCE VOLT- AGES IT CAN BE SHOWN (SEE APPENDIX) THAT THIS RELATIONSHIP IS GIVEN BY (1 61) AS VDS INCREASES, ID INCREASES UNTIL THE DRAIN END OF THE CHANNEL BECOMES PINCHED OFF, AND THEN ID NO LONGER INCREASES THIS PINCH-OFF OCCURS FOR , OR APPROXIMATELY, (1 62) RIGHT AT THE EDGE OF PINCH-OFF, THE DRAIN CURRENT RESULTING FROM (1 61) AND THE DRAIN CURRENT IN THE ACTIVE REGION (WHICH, TO A FIRST-ORDER APPROXIMATION, IS CONSTANT WITH RESPECT TO ) MUST HAVE THE SAME VALUE THEREFORE, THE ACTIVE REGION EQUATION CAN BE FOUND BY SUBSTITUTING (1 62) INTO (1 61), RESULTING IN (1 63) FOR , THE CURRENT STAYS CONSTANT AT THE VALUE GIVEN BY (1 63), IGNORING SECOND-ORDER EFFECTS SUCH AS CHANNEL-LENGTH MODULATION THIS EQUATION IS PERHAPS THE MOST IMPORTANT ONE THAT DESCRIBES THE LARGE-SIGNAL OPERATION OF A MOS TRAN- SISTOR IT SHOULD BE NOTED HERE THAT (1 63) REPRESENTS A SQUARE-LAW CURRENT–VOLTAGE RELATIONSHIP FOR A MOS TRANSISTOR IN THE ACTIVE REGION IN THE CASE OF A BJT TRAN- SISTOR, AN EXPONENTIAL CURRENT–VOLTAGE RELATIONSHIP EXISTS IN THE ACTIVE REGION AS JUST MENTIONED, (1 63) IMPLIES THAT THE DRAIN CURRENT, ID, IS INDEPENDENT OF THE DRAIN-SOURCE VOLTAGE THIS INDEPENDENCE IS ONLY TRUE TO A FIRST-ORDER APPROXIMATION THE MAJOR SOURCE OF ERROR IS DUE TO THE CHANNEL LENGTH SHRINKING AS VDS INCREASES TO SEE THIS EFFECT, CONSIDER FIG 1 15, WHICH SHOWS A CROSS SECTION OF A TRANSISTOR IN THE VEFF 100 MV > 200 MV VGS 100 MV VTN ID ?NCOX W L ----- ? ? ? ? ? ? VGS VTN – ( )VDS VDS – = VDG VTN – = VDS VGS VTN – VEFF = = VDS ID ?NCOX W L ----- ? ? ? ? ? ? VGS VTN – ( ) CHANNEL LENGTH SHORTENING FOR VDS VEFF > N+ N+ VS + ? L PINCH-OFF REGION ID QNA ------------- = M/ V NA ND >> NA VDS VGS VTN – VEFF = = ID ID-SAT ?ID ?L ------- ? ? ? ? ? ? ? ? ?L ?VDS ------------ ? ? ? ? ? ? ?VDS ID-SAT + + ----------------------------------------------- + ? ? ? ? ? ? ? + = ID-SAT VDS VEFF = ?L ?VDS ? ?XD – ?VDS ? = ID ?NCOX W L ----- ? ? ? ? ? ? VGS VTN – ( ) 2 ID VERSUS VDS FOR DIFFERENT VALUES OF VGS 25 ELECTRONS/M 22 HOLES/M × = ?NCOX 270 ?A/V = W L ? 5 ?M/0 5 ?M = VGS 0 8 V = 0 45 V VDS VEFF = ? ID VDS 0 5 V KDS – × M/ V = = ? ? × -------------------------------------------------- 0 171 V ( ) 2 165 ?A × + ( ) × 180 ?A = = THE LOW-FREQUENCY, SMALL-SIGNAL MODEL FOR AN ACTIVE MOS TRANSISTOR VG VGS GMVGS VD GSVSB RDS VS ID IS GMVGS GM ?ID ?VGS ------------ = ID ?NCOX W L ----- ? ? ? ?VGS VTN – ( ) ?NCOX W L ----- ? ? ? ?VEFF = = GM ?ID ?VGS ------------ ?NCOXW L ----- VGS VTN – ( ) ?NCOXW L -----VEFF = = = GM ?NCOXW L -----VEFF = VEFF VEFF VGS VTN – ? VEFF ID VGS VGS VTN 2ID ?NCOX W L ? ( ) -------------------------------- + = VEFF VEFF VGS VTN – 2ID ?NCOX W L ? ( ) -------------------------------- = = GM THE DRAIN CURRENT FOR A PARTICULAR NMOS DEVICE WITH AN ASPECT RATIO IS PLOTTED IN FIG 1 18(A) VERSUS FOR CONSTANT DRAIN, SOURCE, AND BODY VOLTAGES FROM THIS DATA, ESTIMATE AND SOLUTION TAKING THE DERIVATIVE OF FIG 1 18(A) GIVES THE PLOT OF IN FIG 1 18(B) BASED ON THE SQUARE-LAW EQUATION (1 74), THIS PLOT SHOULD BE LINEAR IN THE ACTIVE REGION INTERSECTING THE LINE AT HENCE, EXTRAPOLATING THE LINEAR PORTION OF THE CURVE IN FIG 1 18(B) PROVIDES AN INTERSECTION AT IN THIS CASE, FURTHERMORE, (1 73) SHOWS THAT THE SLOPE OF THE VERSUS CURVE SHOULD BE IN ACTIVE OPERATION IN FIG 1 18(B) THIS SLOPE IS APPROXIMATELY WHICH TRANSLATES TO A VALUE OF THESE ARE APPROXIMATE VALUES, PARTICULARLY SINCE (1 74) IS DERIVED WITHOUT CONSIDERING CHANNEL-LENGTH MODULATION HOWEVER, THESE VALUES ARE VERY USEFUL DURING DESIGN FOR QUICKLY AND ROUGHLY ESTIMAT- ING THE DEVICE SIZES, CURRENTS AND VOLTAGES REQUIRED TO OBTAIN A DESIRED THE SECOND VOLTAGE-CONTROLLED CURRENT-SOURCE IN FIG 1 17, SHOWN AS , MODELS THE BODY EFFECT ON THE SMALL-SIGNAL DRAIN CURRENT, ID WHEN THE SOURCE IS CONNECTED TO SMALL-SIGNAL GROUND, OR WHEN ITS VOLTAGE DOES NOT CHANGE APPRECIABLY, THEN THIS CURRENT SOURCE CAN BE IGNORED WHEN THE BODY EFFECT CANNOT BE IGNORED, WE HAVE (1 79) 14 WHEREAS IT IS PROPORTIONAL TO IC FOR A BJT GM 2?NCOXW L -----ID = ID GM GM 2ID VEFF ------- = KEY POINT: THE SQUARE-ROOT RELA- TIONSHIP FOR TRANSCONDUCTANCE IS USE- FUL FOR CIRCUIT ANALYSIS WHEN DEVICE SIZES ARE FIXED HOWEVER, THE SIM- PLER EXPRESSION GM = 2ID/VEFF IS USE- FUL DURING INITIAL CIRCUIT DESIGN WHEN TRANSISTOR SIZES ARE YET TO BE DETERMINED GM 2?NCOX W L ? ( )ID = ?NCOX W L ? ID VEFF W L ? ( ) ?NCOX VTN W L ? = VGS ?NCOX VTN GM ?ID ?VGS ? = GM = VEFF = VGS VTN = VTN 450 MV ? GM VGS ?NCOX W L ? ( ) 2 7 MA/V ?NCOX 270 ?A/V FROM (1 72) WE HAVE (1 80) USING (1 69), WHICH GIVES AS (1 81) WE HAVE (1 82) THE NEGATIVE SIGN OF (1 80) IS ELIMINATED BY SUBTRACTING THE CURRENT FROM THE MAJOR COMPONENT OF THE DRAIN CURRENT, , AS SHOWN IN FIG 1 17 THUS, USING (1 80) AND (1 82), WE HAVE (1 83) NOTE THAT ALTHOUGH IS NONZERO FOR , IF THE SOURCE IS CONNECTED TO THE BULK IS ZERO AND MAY BE EXCLUDED FROM THE MODEL HOWEVER, IF THE SOURCE HAPPENS TO BE BIASED AT THE SAME POTENTIAL AS THE BULK BUT IS NOT DIRECTLY CONNECTED TO IT, THEN THE EFFECT OF SHOULD BE TAKEN INTO ACCOUNT SINCE THERE MAY BE NONZERO SMALL SIGNALS, THE RESISTOR, RDS, SHOWN IN FIG 1 17, ACCOUNTS FOR THE FINITE OUTPUT IMPEDANCE (I E , IT MODELS THE CHANNEL- LENGTH MODULATION AND ITS EFFECT ON THE DRAIN CURRENT DUE TO CHANGES IN ) USING (1 67), REPEATED HERE FOR CONVENIENCE, (1 84) ESTIMATION OF AND FROM TRANSISTOR VOLTAGE–CURRENT DATA VTN ?NCOX VGS (V) ID (MA) VGS (V) GM (MA/V) (A) (B) VTN 0 45 V = INTERSECTION AT LINEAR SLOPE IS ?NCOX W L ? ( ) 2 7 MA/V ? VSB 2?F + 2?F – ( ) + = ?VTN ?VSB ----------- ? 2 VSB 2?F + ---------------------------------- = GSVS GMVGS GS ? GM 2 VSB 2?F + ---------------------------------- = GS VSB = VSB GS GS VSB VDS ID ?NCOX W L ----- ? ? ? ?VGS VTN – ( ) 2 ? VDS VEFF – ( ) + [ ] = DERIVE THE LOW-FREQUENCY MODEL PARAMETERS FOR AN N-CHANNEL TRANSISTOR THAT HAS DOPING CONCENTRATIONS OF , , , W/L = , , , AND ASSUME AND WHAT IS THE NEW VALUE OF IF THE DRAIN-SOURCE VOLTAGE IS INCREASED BY 0 5 V? SOLUTION SINCE THESE PARAMETERS ARE THE SAME AS IN EXAMPLE 1 8, WE HAVE THE FERMI POTENTIAL OF THE BODY AT ROOM TEMPERATURE WITH IS , AND FROM (1 83) WE HAVE NOTE THAT THIS SOURCE-BULK TRANSCONDUCTANCE VALUE IS ABOUT 1/9TH THAT OF THE GATE-SOURCE TRANSCONDUCTANCE FOR , WE USE (1 86) TO FIND RDS ----- GDS ?ID ?VDS ------------ ? ?NCOX ? ? ? ?W L ----- ? ? ? ?VGS VTN – ( ) ?ID-SAT ?ID ? = = = = ? ID-SAT RDS QNA ------------- = KEY POINT: SMALL SIGNAL RDS IS PROPORTIONAL TO L/ID RDS L ID ? ND = NA × HOLES/M = ?NCOX 270 ?A V ? = 5 ?M 0 5 ?M ? VGS 0 8 V = VTN 0 45 V = VDS VEFF = ? 0 25 V = VSB 0 5 V = RDS GM 2ID VEFF 165 ?A × 0 35 V ---------------------------- 0 94 MA V ? = = = NA PLOTTED IN FIG 1 19(A) IS THE DRAIN CURRENT OF A PARTICULAR NMOS DEVICE VERSUS ITS WITH CONSTANT GATE, SOURCE, AND BODY VOLTAGES FROM THIS DATA, ESTIMATE THE DEVICE PARAMETER SOLUTION FIRST, REARRANGE (1 85) INTO HENCE, A PLOT OF VERSUS FOR A CONSTANT VALUE OF WILL BE ROUGHLY FLAT IN STRONG INVERSION PROVIDING A ROUGH ESTIMATE OF THIS IS DONE FOR THE PRESENT EXAMPLE IN FIG 1 19(B) YIELDING A VALUE OF ESTIMATES OBTAINED IN THIS WAY ARE ONLY APPROXIMATE SINCE IS SUBJECT TO MANY HIGHER-ORDER EFFECTS, ESPECIALLY AT SHORT CHANNEL LENGTHS WHERE MAY CHANGE BY 50% OR EVEN MORE RDS – × × -------------------------------------------- 35 K? = = VEFF 0 35 V = VDS ? ? 0 137 V – = = RDS RDS ID-SAT ---------- = = GDS ID ? ID ? VDS ? ? ( ) ID ? = VDS VGS ? ? 0 45 V – = RDS ? ESTIMATION OF FROM TRANSISTOR VOLTAGE–CURRENT DATA ? VDS (V) ID (MA) VDS (V) GDS ID ? (V – ) (A) (B) ? 0 45 V – = ACTIVE REGION HIGH-FREQUENCY SMALL-SIGNAL MODELLING IN THE ACTIVE REGION A HIGH-FREQUENCY MODEL OF A MOSFET IN THE ACTIVE REGION IS SHOWN IN FIG 1 21 MOST OF THE CAPACITORS IN THE SMALL-SIGNAL MODEL ARE RELATED TO THE PHYSICAL TRANSISTOR SHOWN IN FIG 1 22 IS A CROSS SECTION OF A MOS TRANSISTOR, WHERE THE PARASITIC CAPACITANCES ARE SHOWN AT THE APPROPRIATE LOCATIONS THE LARGEST CAPACITOR IN FIG 1 22 IS THIS CAPACITANCE IS PRIMARILY DUE TO THE CHANGE IN CHANNEL CHARGE AS A RESULT OF A CHANGE IN VGS IT CAN BE SHOWN [TSIVIDIS, 1987] THAT CGS IS APPROXIMATELY GIVEN BY (1 89) VG VS VD RS THE SMALL-SIGNAL, LOW-FREQUENCY T MODEL FOR AN ACTIVE MOS TRANSISTOR (THE BODY EFFECT IS NOT MODELLED) RS RS GM RS – × -------------------------- 1 06 K? = = = RDS CGS CGS A CROSS SECTION OF AN N-CHANNEL MOS TRANSISTOR SHOWING THE SMALL-SIGNAL CAPACITANCES CGS CGD VSB = P+ FIELD CS-SW P– SUBSTRATE LOV CD-SW N+ VGS > VTN VDG > –VTN C?SB C?DB LOV CGS WLCOX COV + = – × = PF ?M ( ) – × PF/ ?M ( ) – × PF ?M ? = W 100 ?M = L 2 ?M = 4 ?M AS = AD 400 ?M (