UNIVERSAL SERIAL BUS SPECIFICATION

By KAREN MILLER

MOTIVATION OBJECTIVE OF THE SPECIFICATION SCOPE OF THE DOCUMENT USB PRODUCT COMPLIANCE DOCUMENT ORGANIZATION GOALS FOR THE UNIVERSAL SERIAL BUS TAXONOMY OF APPLICATION SPACE FEATURE LIST USB SYSTEM DESCRIPTION BUS TOPOLOGY PHYSICAL INTERFACE ELECTRICAL MECHANICAL POWER POWER DISTRIBUTION POWER MANAGEMENT BUS PROTOCOL ROBUSTNESS ERROR DETECTION ERROR HANDLING SYSTEM CONFIGURATION ATTACHMENT OF USB DEVICES REMOVAL OF USB DEVICES BUS ENUMERATION DATA FLOW TYPES CONTROL TRANSFERS BULK TRANSFERS INTERRUPT TRANSFERS ISOCHRONOUS TRANSFERS ALLOCATING USB BANDWIDTH USB DEVICES DEVICE CHARACTERIZATIONS DEVICE DESCRIPTIONS USB HOST: HARDWARE AND SOFTWARE ARCHITECTURAL EXTENSIONS IMPLEMENTER VIEWPOINTS USB HOST PHYSICAL BUS TOPOLOGY LOGICAL BUS TOPOLOGY CLIENT SOFTWARE-TO-FUNCTION RELATIONSHIP USB COMMUNICATION FLOW DEVICE ENDPOINTS PIPES FRAMES AND MICROFRAMES TRANSFER TYPES TABLE CALCULATION EXAMPLES CONTROL TRANSFER DATA FORMAT CONTROL TRANSFER DIRECTION CONTROL TRANSFER PACKET SIZE CONSTRAINTS CONTROL TRANSFER BUS ACCESS CONSTRAINTS CONTROL TRANSFER DATA SEQUENCES ISOCHRONOUS TRANSFER DATA FORMAT ISOCHRONOUS TRANSFER DIRECTION ISOCHRONOUS TRANSFER PACKET SIZE CONSTRAINTS ISOCHRONOUS TRANSFER BUS ACCESS CONSTRAINTS ISOCHRONOUS TRANSFER DATA SEQUENCES INTERRUPT TRANSFER DATA FORMAT INTERRUPT TRANSFER DIRECTION INTERRUPT TRANSFER PACKET SIZE CONSTRAINTS INTERRUPT TRANSFER BUS ACCESS CONSTRAINTS INTERRUPT TRANSFER DATA SEQUENCES BULK TRANSFER DATA FORMAT BULK TRANSFER DIRECTION BULK TRANSFER PACKET SIZE CONSTRAINTS BULK TRANSFER BUS ACCESS CONSTRAINTS BULK TRANSFER DATA SEQUENCES HIGH-SPEED, HIGH BANDWIDTH ENDPOINTS HIGH BANDWIDTH INTERRUPT ENDPOINTS HIGH BANDWIDTH ISOCHRONOUS ENDPOINTS SPLIT TRANSACTIONS BUS ACCESS FOR TRANSFERS TRANSFER MANAGEMENT TRANSACTION TRACKING CALCULATING BUS TRANSACTION TIMES CALCULATING BUFFER SIZES IN FUNCTIONS AND SOFTWARE BUS BANDWIDTH RECLAMATION SPECIAL CONSIDERATIONS FOR ISOCHRONOUS TRANSFERS EXAMPLE NON-USB ISOCHRONOUS APPLICATION USB CLOCK MODEL CLOCK SYNCHRONIZATION ISOCHRONOUS DEVICES DATA PREBUFFERING SOF TRACKING BUFFERING FOR RATE MATCHING ARCHITECTURAL OVERVIEW KEYED CONNECTOR PROTOCOL CABLE CABLE ASSEMBLY STANDARD DETACHABLE CABLE ASSEMBLIES HIGH-/FULL-SPEED CAPTIVE CABLE ASSEMBLIES LOW-SPEED CAPTIVE CABLE ASSEMBLIES PROHIBITED CABLE ASSEMBLIES CONNECTOR MECHANICAL CONFIGURATION AND MATERIAL REQUIREMENTS USB ICON LOCATION USB CONNECTOR TERMINATION DATA SERIES “A” AND SERIES “B” RECEPTACLES SERIES “A” AND SERIES “B” PLUGS CABLE MECHANICAL CONFIGURATION AND MATERIAL REQUIREMENTS DESCRIPTION CONSTRUCTION ELECTRICAL CHARACTERISTICS CABLE ENVIRONMENTAL CHARACTERISTICS LISTING ELECTRICAL, MECHANICAL, AND ENVIRONMENTAL COMPLIANCE STANDARDS APPLICABLE DOCUMENTS USB GROUNDING PCB REFERENCE DRAWINGS SIGNALING USB DRIVER CHARACTERISTICS DATA SIGNAL RISE AND FALL, EYE PATTERNS CABLE SKEW RECEIVER CHARACTERISTICS DEVICE SPEED IDENTIFICATION INPUT CHARACTERISTICS SIGNALING LEVELS DATA ENCODING/DECODING BIT STUFFING SYNC PATTERN DATA SIGNALING RATE FRAME INTERVAL DATA SOURCE SIGNALING HUB SIGNALING TIMINGS RECEIVER DATA JITTER CABLE DELAY CABLE ATTENUATION BUS TURN-AROUND TIME AND INTER-PACKET DELAY MAXIMUM END-TO-END SIGNAL DELAY TEST MODE SUPPORT CLASSES OF DEVICES VOLTAGE DROP BUDGET POWER CONTROL DURING SUSPEND/RESUME DYNAMIC ATTACH AND DETACH PHYSICAL LAYER REGULATORY REQUIREMENTS BUS TIMING/ELECTRICAL CHARACTERISTICS TIMING WAVEFORMS BYTE/BIT ORDERING SYNC FIELD PACKET FIELD FORMATS PACKET IDENTIFIER FIELD ADDRESS FIELDS FRAME NUMBER FIELD DATA FIELD CYCLIC REDUNDANCY CHECKS PACKET FORMATS TOKEN PACKETS SPLIT TRANSACTION SPECIAL TOKEN PACKETS START-OF-FRAME PACKETS DATA PACKETS HANDSHAKE PACKETS HANDSHAKE RESPONSES TRANSACTION PACKET SEQUENCES NAK LIMITING VIA PING FLOW CONTROL BULK TRANSACTIONS INTERRUPT TRANSACTIONS ISOCHRONOUS TRANSACTIONS DATA TOGGLE SYNCHRONIZATION AND RETRY INITIALIZATION VIA SETUP TOKEN SUCCESSFUL DATA TRANSACTIONS DATA CORRUPTED OR NOT ACCEPTED CORRUPTED ACK HANDSHAKE LOW-SPEED TRANSACTIONS ERROR DETECTION AND RECOVERY PACKET ERROR CATEGORIES BUS TURN-AROUND TIMING FALSE EOPS BABBLE AND LOSS OF ACTIVITY RECOVERY USB DEVICE STATES VISIBLE DEVICE STATES GENERIC USB DEVICE OPERATIONS DYNAMIC ATTACHMENT AND REMOVAL ADDRESS ASSIGNMENT CONFIGURATION DATA TRANSFER REQUEST PROCESSING REQUEST ERROR USB DEVICE REQUESTS BMREQUESTTYPE BREQUEST WVALUE WINDEX WLENGTH STANDARD DEVICE REQUESTS CLEAR FEATURE GET CONFIGURATION GET DESCRIPTOR GET INTERFACE GET STATUS SET ADDRESS SET CONFIGURATION SET DESCRIPTOR SET FEATURE SET INTERFACE SYNCH FRAME DESCRIPTORS STANDARD USB DESCRIPTOR DEFINITIONS DEVICE DEVICE_QUALIFIER OTHER_SPEED_CONFIGURATION INTERFACE ENDPOINT STRING DEVICE CLASS DEFINITIONS INTERFACE(S) AND ENDPOINT USAGE REQUESTS OVERVIEW OF THE USB HOST OVERVIEW CONTROL MECHANISMS DATA FLOW COLLECTING STATUS AND ACTIVITY STATISTICS ELECTRICAL INTERFACE CONSIDERATIONS HOST CONTROLLER REQUIREMENTS STATE HANDLING SERIALIZER/DESERIALIZER FRAME AND MICROFRAME GENERATION DATA PROCESSING PROTOCOL ENGINE TRANSMISSION ERROR HANDLING REMOTE WAKEUP ROOT HUB HOST SYSTEM INTERFACE OVERVIEW OF SOFTWARE MECHANISMS DEVICE CONFIGURATION RESOURCE MANAGEMENT DATA TRANSFERS COMMON DATA DEFINITIONS HOST CONTROLLER DRIVER UNIVERSAL SERIAL BUS DRIVER USBD OVERVIEW USBD COMMAND MECHANISM REQUIREMENTS USBD PIPE MECHANISMS MANAGING THE USB VIA THE USBD MECHANISMS PASSING USB PREBOOT CONTROL TO THE OPERATING SYSTEM OPERATING SYSTEM ENVIRONMENT GUIDES HUB ARCHITECTURE HUB CONNECTIVITY HUB FRAME/MICROFRAME TIMER HIGH-SPEED MICROFRAME TIMER RANGE FULL-SPEED FRAME TIMER RANGE FRAME/MICROFRAME TIMER SYNCHRONIZATION MICROFRAME JITTER RELATED TO FRAME JITTER EOF1 AND EOF2 TIMING POINTS HOST BEHAVIOR AT END-OF-FRAME FULL-/LOW-SPEED LATEST HOST PACKET FULL-/LOW-SPEED PACKET NULLIFICATION FULL-/LOW-SPEED TRANSACTION COMPLETION PREDICTION INTERNAL PORT INACTIVE SUSPEND DELAY FULL SUSPEND (FSUS) GENERATE RESUME (GRESUME) DOWNSTREAM FACING PORTS DOWNSTREAM FACING PORT STATE DESCRIPTIONS DISCONNECT DETECT TIMER PORT INDICATOR UPSTREAM FACING PORT FULL-SPEED HIGH-SPEED RECEIVER TRANSMITTER HUB REPEATER HIGH-SPEED PACKET CONNECTIVITY HUB REPEATER STATE MACHINE WAIT FOR START OF PACKET FROM UPSTREAM PORT (WFSOPFU) WAIT FOR END OF PACKET FROM UPSTREAM PORT (WFEOPFU) WAIT FOR START OF PACKET (WFSOP) WAIT FOR END OF PACKET (WFEOP) BUS STATE EVALUATION PORT ERROR SPEED DETECTION COLLISION LOW-SPEED PORT BEHAVIOR SUSPEND AND RESUME 11 10 HUB RESET BEHAVIOR 11 11 HUB PORT POWER CONTROL 11 11 1 MULTIPLE GANGS 11 12 HUB CONTROLLER 11 12 1 ENDPOINT ORGANIZATION 11 12 2 HUB INFORMATION ARCHITECTURE AND OPERATION 11 12 3 PORT CHANGE INFORMATION PROCESSING 11 12 4 HUB AND PORT STATUS CHANGE BITMAP 11 12 5 OVER-CURRENT REPORTING AND RECOVERY 11 12 6 ENUMERATION HANDLING 11 13 HUB CONFIGURATION TRANSACTION TRANSLATOR 11 14 1 OVERVIEW 11 14 2 TRANSACTION TRANSLATOR SCHEDULING 11 15 SPLIT TRANSACTION NOTATION INFORMATION 11 16 COMMON SPLIT TRANSACTION STATE MACHINES 11 16 1 HOST CONTROLLER STATE MACHINE 11 16 2 TRANSACTION TRANSLATOR STATE MACHINE 11 17 BULK/CONTROL TRANSACTION TRANSLATION OVERVIEW 11 17 1 BULK/CONTROL SPLIT TRANSACTION SEQUENCES 11 17 2 BULK/CONTROL SPLIT TRANSACTION STATE MACHINES 11 17 3 BULK/CONTROL SEQUENCING 11 17 4 BULK/CONTROL BUFFERING REQUIREMENTS 11 17 5 OTHER BULK/CONTROL DETAILS 11 18 PERIODIC SPLIT TRANSACTION PIPELINING AND BUFFER MANAGEMENT 11 18 1 BEST CASE FULL-SPEED BUDGET 11 18 2 TT MICROFRAME PIPELINE 11 18 3 GENERATION OF FULL-SPEED FRAMES 11 18 4 HOST SPLIT TRANSACTION SCHEDULING REQUIREMENTS 11 18 5 TT RESPONSE GENERATION 11 18 6 TT PERIODIC TRANSACTION HANDLING REQUIREMENTS 11 18 7 TT TRANSACTION TRACKING 11 18 8 TT COMPLETE-SPLIT TRANSACTION STATE SEARCHING 11 19 APPROXIMATE TT BUFFER SPACE REQUIRED 11 20 INTERRUPT TRANSACTION TRANSLATION OVERVIEW 11 20 1 INTERRUPT SPLIT TRANSACTION SEQUENCES 11 20 2 INTERRUPT SPLIT TRANSACTION STATE MACHINES 11 20 3 INTERRUPT OUT SEQUENCING 11 20 4 INTERRUPT IN SEQUENCING 11 21 ISOCHRONOUS TRANSACTION TRANSLATION OVERVIEW 11 21 1 ISOCHRONOUS SPLIT TRANSACTION SEQUENCES 11 21 2 ISOCHRONOUS SPLIT TRANSACTION STATE MACHINES 11 21 3 ISOCHRONOUS OUT SEQUENCING 11 21 4 ISOCHRONOUS IN SEQUENCING 11 22 TT ERROR HANDLING 11 22 1 LOSS OF TT SYNCHRONIZATION WITH HS SOFS 11 22 2 TT FRAME AND MICROFRAME TIMER SYNCHRONIZATION REQUIREMENTS 11 23 DESCRIPTORS 11 23 1 STANDARD DESCRIPTORS FOR HUB CLASS 11 23 2 CLASS-SPECIFIC DESCRIPTORS 11 24 REQUESTS 11 24 1 STANDARD REQUESTS 11 24 2 CLASS-SPECIFIC REQUESTS

ISBN978-93-7785-163-7
Copyright Year2027
Pages452
Price$275.99
LanguageEnglish
FormatPDF
CategoryELECTRONICS