TELECOMMUNICATIONS TRANSMISSION ENGINEERING
CONTENTS WIRELESS COMMUNICATIONS AND TRANSCEIVERS: AN OVERVIEW WIRELESS AND MOBILE COMMUNICATIONS INTEGRATED CIRCUIT TECHNOLOGIES FOR WIRELESS SYSTEMS TRANSCEIVERS FOR WIRELESS AND MOBILE COMMUNICATIONS CHALLENGING TOPICS IN COMMUNICATION CIRCUITS AND SYSTEMS TRANSCEIVER ARCHITECTURE AND SYSTEM-LEVEL DESIGN RF, IF AND ANALOGUE BASEBAND CIRCUITS AND SUBSYSTEMS DESIGN OPTIMISATION AND AUTOMATIC TESTING TECHNIQUES SUMMARY OF CHAPTERS NON-COMPLEX SIGNAL PROCESSING IN A LOW-IF RECEIVER INTRODUCTION EVOLUTION OF INTEGRATED RECEIVER ARCHITECTURES THE CONVENTIONAL SUPERHET ARCHITECTURE THE ZERO-IF ARCHITECTURE LOW-IF ARCHITECTURE DIGITISING A CONVENTIONAL LOW-IF ARCHITECTURE PERFORMANCE REQUIREMENTS RECEIVER DIMENSIONS THE CHANGE TO NON-COMPLEX SIGNAL PROCESSING POLYPHASE IMAGE-REJECTION ?LTER MAKE-COMPLEX CHANNEL ?LTER MODULATOR ADC SYSTEM SIMULATIONS INCORPORATION IN A DUAL-MODE RECEIVER CONCLUSIONS REFERENCES A RECON?GURABLE BASEBAND CHAIN FOR 3G WIRELESS RECEIVERS LOW-NOISE FULLY DIFFERENTIAL VOLTAGE BUFFER DIFFERENTIAL DIFFERENCE AMPLI?ER-BASED FULLY DIFFERENTIAL BUFFER MOS REALISATION OF A FULLY DIFFERENTIAL DDA WIDE-RANGE LOW-NOISE FDB BASED ON THE DDA HIGHLY LINEAR DDA-BASED ?LTER SECTION TUNEABLE ?LTER SECTION VARIABLE GAIN AMPLI?ER RECON?GURABLE BASEBAND CHAIN FOR 3G RECEIVERS FIELD-PROGRAMMABLE AND RECON?GURABLE ANALOGUE AND MIXED-SIGNAL ARRAYS FIELD-PROGRAMMABLE ANALOGUE ARRAYS (FPAA) GENERAL ARCHITECTURE CON?GURABLE ANALOGUE BLOCKS (CABS) CAD DESIGN PROCEDURE USING FPAAS GENERAL DESIGN ISSUES FOR FPAA ADVANCED CIRCUIT TECHNIQUES FOR FPAA FPAA APPLICATIONS COMMERCIAL FPAA PRODUCTS LATTICE SEMICONDUCTOR’S PROGRAMMABLE ANALOGUE CIRCUITS (ISPPAC) ZETEX SEMICONDUCTOR’S TRAC (TOTALLY RECON?GURABLE ANALOGUE CIRCUIT) ANADIGM ?ELD PROGRAMMABLE ANALOGUE ARRAY (AN10E40) CONTINUOUS-TIME CMOS OTA-C FPAA FOR HIGH FREQUENCIES PROGRAMMABLE OTA PROGRAMMABLE CAPACITOR ARRAY CON?GURABLE ANALOGUE BLOCK USING PROGRAMMABLE OTAS AND CAPACITORS FINE TUNING OF PARAMETERS FPAA USING CABS AND ITS APPLICATION IN OTA-C ?LTER DESIGN FPMA AND SOPC FPMA SOC AND SOPC COMMERCIAL MIXED-SIGNAL SOPC: SIDSA FIPSOC RECON?GURABLE UNIVERSAL TRANSCEIVERS USING FPAAS UNIVERSAL TRANSCEIVERS FOR DIFFERENT STANDARDS RECON?GURABLE TRANSCEIVERS USING FPAA A LOW-POWER, LOW-VOLTAGE BLUETOOTH CHANNEL ?LTER USING CLASS AB CMOS TRANSCONDUCTORS FILTER SYNTHESIS COMPLEX ?LTERS BLUETOOTH ?LTER SYNTHESIS CLASS AB CMOS TRANSCONDUCTOR CELL DEVELOPMENT FREQUENCY TUNING FILTER DESIGN PERFORMANCE DESIGN AND AUTOMATIC TUNING OF INTEGRATED CONTINUOUS-TIME ?LTERS FILTERS IN TRANSCEIVERS AND THE NEED FOR TUNING FILTER REQUIREMENTS FOR WIRELESS TRANSCEIVERS THE NEED FOR ON-CHIP TUNING FILTER ARCHITECTURES AND DESIGN METHODS SECOND-ORDER CASCADE ARCHITECTURE MULTIPLE-LOOP FEEDBACK ARCHITECTURE LC LADDER SIMULATION OTA-C ?LTERS MOSFET-C ?LTERS ACTIVE-LC ?LTERS SWITCHED ARRAYS FOR ?LTER TUNING ON-CHIP TUNING OF CONTINUOUS-TIME ?LTERS FREQUENCY TUNING AND Q TUNING ON-LINE AND OFF-LINE TUNING MASTER–SLAVE TUNING FREQUENCY TUNING METHODS Q TUNING TECHNIQUES TUNING OF HIGH-ORDER LEAP-FROG ?LTERS LOW-VOLTAGE INTEGRATED RF CMOS MODULES AND FRONTEND FOR 5 GHZ AND BEYOND A VERSATILE LOW-VOLTAGE CMOS LNA TOPOLOGY SINGLE-TRANSISTOR ARCHITECTURE CONVENTIONAL CASCODE LNA ARCHITECTURE LC-COUPLED ARCHITECTURE FOLDED CASCODE ARCHITECTURE GAIN CONTROL IN THE FOLDED CASCODE STRUCTURE FREQUENCY CONTROL IN THE FOLDED CASCODE STRUCTURE DESIGN EQUATIONS AND OPTIMISATION MEASUREMENT RESULTS – STAND-ALONE LNAS A CMOS VCO ARCHITECTURE SUITABLE FOR SUB-1 VOLT GHZ-RANGE APPLICATIONS THE COMPLEMENTARY DIFFERENTIAL LC STRUCTURE PROPOSED LOW-VOLTAGE VCO CIRCUIT ARCHITECTURE VCO DETAILED CIRCUITRY AND DESIGN GUIDELINES VCO EXPERIMENTAL RESULTS A VERY LOW-VOLTAGE (0 8 V) 5 GHZ CMOS RECEIVER FRONTEND THE DIFFERENTIAL LNA THE MIXER THE QUADRATURE VOLTAGE-CONTROLLED OSCILLATOR MEASURED CHARACTERISTICS OF THE RECEIVER DESIGN OF INTEGRATED CMOS POWER AMPLI?ERS FOR WIRELESS TRANSCEIVERS POWER AMPLI?ERS (PAS): CONCEPTS AND CHALLENGES CONJUGATE MATCH AND LOAD-LINE MATCH EFFECT OF THE TRANSISTOR KNEE (PINCH-OFF) VOLTAGE CLASSI?CATION OF POWER AMPLI?ERS POWER AMPLI?ER LINEARISATION SPECTRAL REGROWTH POWER AMPLI?ER CONTROLLABILITY AND STABILITY POWER AMPLI?ER CONTROLLABILITY POWER AMPLI?ER STABILITY ISSUES RECENT PROGRESS IN RF CMOS PA DESIGN PARASITIC-AWARE RF IC DESIGN AND OPTIMISATION ON-CHIP INDUCTOR MODELLING SPIRAL INDUCTORS BOND WIRE INDUCTOR PARASITIC-AWARE OPTIMISATION SIMULATED ANNEALING ADAPTIVE SIMULATED ANNEALING POST-PVT VARIATION OPTIMISATION SIMULATION RESULTS RF CIRCUIT SYNTHESES CLASS-E POWER AMPLI?ER CLASS-E POWER AMPLI?ER OPTIMISATION RESULTS CMOS RF DISTRIBUTED AMPLI?ERS DISTRIBUTED AMPLI?ER OPTIMISATION RESULTS TESTING OF RF, ANALOGUE AND MIXED-SIGNAL CIRCUITS FOR COMMUNICATIONS: AN EMBEDDED APPROACH SOME ANALOGUE PERFORMANCE METRICS AND TEST FUNDAMENTALS 10 2 1 LINEARITY 10 2 2 FREQUENCY RESPONSE 10 2 3 NOISE 10 2 4 OTHER PERFORMANCE METRICS TRANSLATING DESIGN SPECI?CATIONS INTO PRODUCTION TEST PROGRAMMES THE (DIMINISHING) ROLE OF TEST EQUIPMENT 10 4 1 GENERIC ARCHITECTURE OF AUTOMATIC TEST EQUIPMENT 10 4 2 SIGNAL DELIVERY EMBEDDED MIXED-SIGNAL TEST CORES 10 5 1 SIGNAL GENERATION (CIRCULAR MEMORY A) 10 5 2 SIGNAL DIGITISATION (CIRCULAR MEMORY B AND COMPARATOR) 10 5 3 SELF-CHECKING CIRCUIT CONSIDERATIONS AND INSTRUMENT PERFORMANCE EVALUATION 10 6 1 CIRCUIT CONSIDERATIONS 10 6 2 EXPERIMENTAL EVALUATION MEASUREMENT TYPES AND TEST EXAMPLES 10 7 1 DC CURVE-TRACER 10 7 2 SPECTRUM ANALYSER 10 7 3 OSCILLOSCOPE 10 7 4 JITTER MEASUREMENT DEVICE