DIGITAL DESIGN FUNDAMENTALS
CONTENTS C H A P T E R INTRODUCTION DIGITAL HARDWARE STANDARD CHIPS PROGRAMMABLE LOGIC DEVICES CUSTOM-DESIGNED CHIPS THE DESIGN PROCESS STRUCTURE OF A COMPUTER LOGIC CIRCUIT DESIGN IN THIS BOOK DIGITAL REPRESENTATION OF INFORMATION BINARY NUMBERS CONVERSION BETWEEN DECIMAL AND BINARY SYSTEMS ASCII CHARACTER CODE DIGITAL AND ANALOG INFORMATION THEORY AND PRACTICE PROBLEMS REFERENCES C H A P T E R INTRODUCTION TO LOGIC CIRCUITS VARIABLES AND FUNCTIONS INVERSION TRUTH TABLES LOGIC GATES AND NETWORKS ANALYSIS OF A LOGIC NETWORK BOOLEAN ALGEBRA THE VENN DIAGRAM NOTATION AND TERMINOLOGY PRECEDENCE OF OPERATIONS SYNTHESIS USING AND, OR, AND NOT GATES SUM-OF-PRODUCTS AND PRODUCT-OF-SUMS FORMS NAND AND NOR LOGIC NETWORKS DESIGN EXAMPLES THREE-WAY LIGHT CONTROL MULTIPLEXER CIRCUIT NUMBER DISPLAY INTRODUCTION TO CAD TOOLS DESIGN ENTRY LOGIC SYNTHESIS FUNCTIONAL SIMULATION PHYSICAL DESIGN TIMING SIMULATION CIRCUIT IMPLEMENTATION COMPLETE DESIGN FLOW 2 10 INTRODUCTION TO VERILOG STRUCTURAL SPECI?CATION OF LOGIC CIRCUITS BEHAVIORAL SPECI?CATION OF LOGIC CIRCUITS HIERARCHICAL VERILOG CODE HOW NOT TO WRITE VERILOG CODE 2 11 MINIMIZATION AND KARNAUGH MAPS 2 12 STRATEGY FOR MINIMIZATION TERMINOLOGY MINIMIZATION PROCEDURE 2 13 MINIMIZATION OF PRODUCT-OF-SUMS FORMS 2 14 INCOMPLETELY SPECI?ED FUNCTIONS 2 15 MULTIPLE-OUTPUT CIRCUITS 2 16 CONCLUDING REMARKS 2 17 EXAMPLES OF SOLVED PROBLEMS NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS POSITIONAL NUMBER REPRESENTATION UNSIGNED INTEGERS OCTAL AND HEXADECIMAL REPRESENTATIONS ADDITION OF UNSIGNED NUMBERS DECOMPOSED FULL-ADDER RIPPLE-CARRY ADDER DESIGN EXAMPLE SIGNED NUMBERS NEGATIVE NUMBERS ADDITION AND SUBTRACTION ADDER AND SUBTRACTOR UNIT RADIX-COMPLEMENT SCHEMES? ARITHMETIC OVER?OW PERFORMANCE ISSUES FAST ADDERS CARRY-LOOKAHEAD ADDER DESIGN OF ARITHMETIC CIRCUITS USING CAD TOOLS DESIGN OF ARITHMETIC CIRCUITS USING SCHEMATIC CAPTURE DESIGN OF ARITHMETIC CIRCUITS USING VERILOG USING VECTORED SIGNALS USING A GENERIC SPECI?CATION NETS AND VARIABLES IN VERILOG ARITHMETIC ASSIGNMENT STATEMENTS MODULE HIERARCHY IN VERILOG CODE REPRESENTATION OF NUMBERS IN VERILOG CODE MULTIPLICATION ARRAY MULTIPLIER FOR UNSIGNED NUMBERS MULTIPLICATION OF SIGNED NUMBERS OTHER NUMBER REPRESENTATIONS FIXED-POINT NUMBERS FLOATING-POINT NUMBERS BINARY-CODED-DECIMAL REPRESENTATION EXAMPLES OF SOLVED PROBLEMS COMBINATIONAL-CIRCUIT BUILDING BLOCKS MULTIPLEXERS SYNTHESIS OF LOGIC FUNCTIONS USING MULTIPLEXERS MULTIPLEXER SYNTHESIS USING SHANNON’S EXPANSION DECODERS DEMULTIPLEXERS ENCODERS BINARY ENCODERS PRIORITY ENCODERS CODE CONVERTERS ARITHMETIC COMPARISON CIRCUITS VERILOG FOR COMBINATIONAL CIRCUITS THE CONDITIONAL OPERATOR THE IF-ELSE STATEMENT THE CASE STATEMENT THE FOR LOOP VERILOG OPERATORS THE GENERATE CONSTRUCT TASKS AND FUNCTIONS CONCLUDING REMARKS FLIP-FLOPS, REGISTERS, AND COUNTERS BASIC LATCH GATED SR LATCH GATED SR LATCH WITH NAND GATES GATED D LATCH EFFECTS OF PROPAGATION DELAYS EDGE-TRIGGERED D FLIP-FLOPS MASTER-SLAVE D FLIP-FLOP OTHER TYPES OF EDGE-TRIGGERED D FLIP-FLOPS D FLIP-FLOPS WITH CLEAR AND PRESET FLIP-FLOP TIMING PARAMETERS T FLIP-FLOP JK FLIP-FLOP SUMMARY OF TERMINOLOGY REGISTERS SHIFT REGISTER PARALLEL-ACCESS SHIFT REGISTER COUNTERS ASYNCHRONOUS COUNTERS SYNCHRONOUS COUNTERS COUNTERS WITH PARALLEL LOAD 5 10 RESET SYNCHRONIZATION 5 11 OTHER TYPES OF COUNTERS BCD COUNTER RING COUNTER JOHNSON COUNTER REMARKS ON COUNTER DESIGN 5 12 USING STORAGE ELEMENTS WITH CAD TOOLS INCLUDING STORAGE ELEMENTS IN SCHEMATICS USING VERILOG CONSTRUCTS FOR STORAGE ELEMENTS BLOCKING AND NON-BLOCKING ASSIGNMENTS NON-BLOCKING ASSIGNMENTS FOR COMBINATIONAL CIRCUITS FLIP-FLOPS WITH CLEAR CAPABILITY 5 13 USING VERILOG CONSTRUCTS FOR REGISTERS AND COUNTERS FLIP-FLOPS AND REGISTERS WITH ENABLE INPUTS SHIFT REGISTERS WITH ENABLE INPUTS 5 14 DESIGN EXAMPLE REACTION TIMER REGISTER TRANSFER LEVEL (RTL) CODE 5 15 TIMING ANALYSIS OF FLIP-?OP CIRCUITS TIMING ANALYSIS WITH CLOCK SKEW 5 16 CONCLUDING REMARKS 5 17 EXAMPLES OF SOLVED PROBLEMS SYNCHRONOUS SEQUENTIAL CIRCUITS BASIC DESIGN STEPS STATE DIAGRAM STATE TABLE STATE ASSIGNMENT CHOICE OF FLIP-FLOPS AND DERIVATION OF NEXT-STATE AND OUTPUT EXPRESSIONS TIMING DIAGRAM SUMMARY OF DESIGN STEPS STATE-ASSIGNMENT PROBLEM ONE-HOT ENCODING MEALY STATE MODEL DESIGN OF FINITE STATE MACHINES USING CAD TOOLS VERILOG CODE FOR MOORE-TYPE FSMS SYNTHESIS OF VERILOG CODE SIMULATING AND TESTING THE CIRCUIT ALTERNATIVE STYLES OF VERILOG CODE SUMMARY OF DESIGN STEPS WHEN USING CAD TOOLS SPECIFYING THE STATE ASSIGNMENT IN VERILOG CODE SPECI?CATION OF MEALY FSMS USING VERILOG SERIAL ADDER EXAMPLE MEALY-TYPE FSM FOR SERIAL ADDER MOORE-TYPE FSM FOR SERIAL ADDER VERILOG CODE FOR THE SERIAL ADDER STATE MINIMIZATION PARTITIONING MINIMIZATION PROCEDURE INCOMPLETELY SPECI?ED FSMS DESIGN OF A COUNTER USING THE SEQUENTIAL CIRCUIT APPROACH STATE DIAGRAM AND STATE TABLE FOR A MODULO-8 COUNTER IMPLEMENTATION USING D-TYPE FLIP-FLOPS IMPLEMENTATION USING JK-TYPE FLIP-FLOPS EXAMPLE—A DIFFERENT COUNTER FSM AS AN ARBITER CIRCUIT ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS 6 10 ALGORITHMIC STATE MACHINE (ASM) CHARTS 6 11 FORMAL MODEL FOR SEQUENTIAL CIRCUITS 6 12 CONCLUDING REMARKS 6 13 EXAMPLES OF SOLVED PROBLEMS DIGITAL SYSTEM DESIGN BUS STRUCTURE USING TRI-STATE DRIVERS TO IMPLEMENT A BUS USING MULTIPLEXERS TO IMPLEMENT A BUS VERILOG CODE FOR SPECI?CATION OF BUS STRUCTURES SIMPLE PROCESSOR A BIT-COUNTING CIRCUIT SHIFT-AND-ADD MULTIPLIER DIVIDER ARITHMETIC MEAN SORT OPERATION CLOCK SYNCHRONIZATION AND TIMING ISSUES CLOCK DISTRIBUTION ASYNCHRONOUS INPUTS TO FLIP-FLOPS SWITCH DEBOUNCING OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS MULTILEVEL SYNTHESIS FACTORING FUNCTIONAL DECOMPOSITION MULTILEVEL NAND AND NOR CIRCUITS ANALYSIS OF MULTILEVEL CIRCUITS ALTERNATIVE REPRESENTATIONS OF LOGIC FUNCTIONS CUBICAL REPRESENTATION BINARY DECISION DIAGRAMS OPTIMIZATION TECHNIQUES BASED ON CUBICAL REPRESENTATION A TABULAR METHOD FOR MINIMIZATION A CUBICAL TECHNIQUE FOR MINIMIZATION PRACTICAL CONSIDERATIONS ASYNCHRONOUS SEQUENTIAL CIRCUITS ASYNCHRONOUS BEHAVIOR ANALYSIS OF ASYNCHRONOUS CIRCUITS SYNTHESIS OF ASYNCHRONOUS CIRCUITS STATE REDUCTION TRANSITION DIAGRAM EXPLOITING UNSPECI?ED NEXT-STATE ENTRIES STATE ASSIGNMENT USING ADDITIONAL STATE VARIABLES ONE-HOT STATE ASSIGNMENT HAZARDS STATIC HAZARDS DYNAMIC HAZARDS SIGNI?CANCE OF HAZARDS A COMPLETE DESIGN EXAMPLE THE VENDING-MACHINE CONTROLLER COMPUTER AIDED DESIGN TOOLS 10 1 SYNTHESIS NETLIST GENERATION GATE OPTIMIZATION TECHNOLOGY MAPPING 10 2 PHYSICAL DESIGN PLACEMENT ROUTING STATIC TIMING ANALYSIS 10 3 CONCLUDING REMARKS TESTING OF LOGIC CIRCUITS 11 1 FAULT MODEL STUCK-AT MODEL SINGLE AND MULTIPLE FAULTS CMOS CIRCUITS 11 2 COMPLEXITY OF A TEST SET 11 3 PATH SENSITIZING DETECTION OF A SPECI?C FAULT 11 4 CIRCUITS WITH TREE STRUCTURE 11 5 RANDOM TESTS CONTENTS 11 6 TESTING OF SEQUENTIAL CIRCUITS DESIGN FOR TESTABILITY 11 7 BUILT-IN SELF-TEST BUILT-IN LOGIC BLOCK OBSERVER SIGNATURE ANALYSIS BOUNDARY SCAN 11 8 PRINTED CIRCUIT BOARDS TESTING OF PCBS INSTRUMENTATION 11 9 CONCLUDING REMARKS