ESD IN SILICON INTEGRATED CIRCUITS

By Q. KITIA

CONTENTS INTRODUCTION BACKGROUND THE ESD PROBLEM PROTECTING AGAINST ESD OUTLINE OF THE BOOK BIBLIOGRAPHY ESD PHENOMENON ELECTROSTATIC VOLTAGE DISCHARGE ESD STRESS MODELS TEST METHODS HUMAN BODY MODEL (HBM) MACHINE MODEL (MM) CHARGED DEVICE MODEL (CDM) SOCKET DEVICE MODEL (SDM) METROLOGY, CALIBRATION, VERI?CATION TRANSMISSION LINE PULSING (TLP) FAILURE CRITERIA SUMMARY PHYSICS AND OPERATION OF ESD PROTECTION CIRCUIT ELEMENTS RESISTORS DIODES TRANSISTOR OPERATION TRANSISTOR OPERATION UNDER ESD CONDITIONS ELECTROTHERMAL EFFECTS SCR OPERATION CONCLUSION ESD PROTECTION CIRCUIT DESIGN CONCEPTS AND STRATEGY THE QUALITIES OF GOOD ESD PROTECTION ESD PROTECTION DESIGN METHODS SELECTING AN ESD STRATEGY DESIGN AND LAYOUT REQUIREMENTS THICK FIELD DEVICE NMOS TRANSISTORS (FPDS) GATE-COUPLED NMOS (GCNMOS) GATE DRIVEN NMOS (GDNMOS) SCR PROTECTION DEVICE ESD PROTECTION DESIGN SYNTHESIS TOTAL INPUT PROTECTION ESD PROTECTION USING DIODE-BASED DEVICES 6 10 POWER SUPPLY CLAMPS 6 11 BIPOLAR AND BICMOS PROTECTION CIRCUITS 6 12 SUMMARY ADVANCED PROTECTION DESIGN PNP-DRIVEN NMOS (PDNMOS) SUBSTRATE TRIGGERED NMOS (STNMOS) NMOS TRIGGERED NMOS (NTNMOS) ESD FOR MIXED-VOLTAGE I/O CDM PROTECTION SOI TECHNOLOGY HIGH-VOLTAGE TRANSISTORS BICMOS PROTECTION 7 10 RF DESIGNS 7 11 GENERAL I/O PROTECTION SCHEMES 7 12 DESIGN/LAYOUT ERRORS 7 13 SUMMARY FAILURE MODES, RELIABILITY ISSUES, AND CASE STUDIES FAILURE MODE ANALYSIS RELIABILITY AND PERFORMANCE CONSIDERATIONS ADVANCED CMOS INPUT PROTECTION OPTIMIZING THE INPUT PROTECTION SCHEME DESIGNS FOR SPECIAL APPLICATIONS PROCESS EFFECTS ON INPUT PROTECTION DESIGN TOTAL IC CHIP PROTECTION POWER BUS PROTECTION 8 10 INTERNAL CHIP ESD DAMAGE 8 11 STRESS DEPENDENT ESD BEHAVIOR 8 12 FAILURE MODE CASE STUDIES 8 13 SUMMARY IN?UENCE OF PROCESSING ON ESD HIGH CURRENT BEHAVIOR CROSS SECTION OF A MOS TRANSISTOR DRAIN-SOURCE IMPLANT EFFECTS P-WELL EFFECTS N-WELL EFFECTS EPITAXIAL LAYERS AND SUBSTRATES GATE OXIDES SILICIDES 9 10 CONTACTS 9 11 INTERCONNECT AND METALIZATION 9 12 GATE LENGTH DEPENDENCIES 9 13 SILICON-ON-INSULATOR (SOI) 9 14 BIPOLAR TRANSISTORS 9 15 DIODES 9 16 RESISTORS 9 17 RELIABILITY TRADE-OFFS 9 18 SUMMARY 10 DEVICE MODELING OF HIGH CURRENT EFFECTS 10 1 INTRODUCTION 10 2 THE PHYSICS OF ESD DAMAGE 10 3 THERMAL (“SECOND”) BREAKDOWN 10 4 ANALYTICAL MODELS USING THE HEAT EQUATION 10 5 ELECTROTHERMAL DEVICE SIMULATIONS 10 6 CONCLUSION 11 CIRCUIT SIMULATION BASICS, APPROACHES, AND APPLICATIONS 11 1 INTRODUCTION 11 2 MODELING THE MOSFET 11 3 MODELING BIPOLAR JUNCTION TRANSISTORS 11 4 MODELING DIFFUSION RESISTORS 11 5 MODELING PROTECTION DIODES 11 6 SIMULATION OF PROTECTION CIRCUITS 11 7 ELECTROTHERMAL CIRCUIT SIMULATIONS 11 8 CONCLUSION 12 CONCLUSION 12 1 LONG-TERM RELEVANCE OF ESD IN ICS 12 2 STATE-OF-THE-ART FOR ESD PROTECTION 12 3 CURRENT LIMITATIONS 12 4 FUTURE ISSUES