MICROPROCESSOR ARCHITECTURE: FROM SIMPLE PIPELINES TO CHIP MULTIPROCESSORS

By JAMES MOORE

CONTENTS 1 INTRODUCTION 1 1 A QUICK VIEW OF TECHNOLOGICAL ADVANCES 1 2 PERFORMANCE METRICS 1 3 PERFORMANCE EVALUATION 1 4 SUMMARY 1 5 FURTHER READING AND BIBLIOGRAPHICAL NOTES EXERCISES REFERENCES 2 THE BASICS 2 1 PIPELINING 2 2 CACHES 2 3 VIRTUAL MEMORY AND PAGING 2 4 SUMMARY 2 5 FURTHER READING AND BIBLIOGRAPHICAL NOTES 3 SUPERSCALAR PROCESSORS 3 1 FROM SCALAR TO SUPERSCALAR PROCESSORS 3 2 OVERVIEW OF THE INSTRUCTION PIPELINE OF THE DEC ALPHA 3 3 INTRODUCING REGISTER RENAMING, REORDER BUFFER, AND RESERVATION STATIONS 3 4 OVERVIEW OF THE PENTIUM P6 MICROARCHITECTURE 3 5 VLIW/EPIC PROCESSORS 3 6 SUMMARY 3 7 FURTHER READING AND BIBLIOGRAPHICAL NOTES 4 FRONT-END: BRANCH PREDICTION, INSTRUCTION FETCHING, AND REGISTER RENAMING 4 1 BRANCH PREDICTION SIDEBAR: THE DEC ALPHA 21264 BRANCH PREDICTOR 4 2 INSTRUCTION FETCHING 4 3 DECODING 4 4 REGISTER RENAMING (A SECOND LOOK) 4 5 SUMMARY 4 6 FURTHER READING AND BIBLIOGRAPHICAL NOTES PROGRAMMING PROJECTS 5 BACK-END: INSTRUCTION SCHEDULING, MEMORY ACCESS INSTRUCTIONS, AND CLUSTERS 5 1 INSTRUCTION ISSUE AND SCHEDULING (WAKEUP AND SELECT) 5 2 MEMORY-ACCESSING INSTRUCTIONS 5 3 BACK-END OPTIMIZATIONS 5 4 SUMMARY 5 5 FURTHER READING AND BIBLIOGRAPHICAL NOTES PROGRAMMING PROJECT 6 THE CACHE HIERARCHY 6 1 IMPROVING ACCESS TO L1 CACHES 6 2 HIDING MEMORY LATENCIES 6 3 DESIGN ISSUES FOR LARGE HIGHER-LEVEL CACHES 6 4 MAIN MEMORY 6 5 SUMMARY 6 6 FURTHER READING AND BIBLIOGRAPHICAL NOTES 7 MULTIPROCESSORS 7 1 MULTIPROCESSOR ORGANIZATION 7 2 CACHE COHERENCE 7 3 SYNCHRONIZATION 7 4 RELAXED MEMORY MODELS 7 5 MULTIMEDIA INSTRUCTION SET EXTENSIONS 7 6 SUMMARY 7 7 FURTHER READING AND BIBLIOGRAPHICAL NOTES 8 MULTITHREADING AND (CHIP) MULTIPROCESSING 8 1 SINGLE-PROCESSOR MULTITHREADING 8 2 GENERAL-PURPOSE MULTITHREADED CHIP MULTIPROCESSORS 8 3 SPECIAL-PURPOSE MULTITHREADED CHIP MULTIPROCESSORS 8 4 SUMMARY 8 5 FURTHER READING AND BIBLIOGRAPHICAL NOTES 9 CURRENT LIMITATIONS AND FUTURE CHALLENGES 9 1 POWER AND THERMAL MANAGEMENT 9 2 TECHNOLOGICAL LIMITATIONS: WIRE DELAYS AND PIPELINE DEPTHS 9 3 CHALLENGES FOR CHIP MULTIPROCESSORS 9 4 SUMMARY 9 5 FURTHER READING AND BIBLIOGRAPHICAL NOTES